Cypress CY2048WAF user manual

Summary of the content on the page No. 1

CY2048WAF
Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
Features Benefits
• Flash-programmable capacitor tuning array for low • Enables fine-tuning of output clock frequency by
ppm initial frequency clock output adjusting C of the crystal
Load
• Low clock output jitter • Allows multiple programming opportunities to correct
errors, and control excess inventory
— 4 ps typ. RMS period jitter
• Enables programming of output frequency after
— ±30 ps typ. peak-to-peak per

Summary of the content on the page No. 2

CY2048WAF Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0)) Name Pad Number Description X coordinate ( µm) Y coordinate ( µm) VDD 1 Voltage Supply –360.8 353.7 XOUT 2 Oscillator Drain –360.8 134.1 XIN 3 Oscillator Gate –360.8 –42.6 PD#/OE 4 Programmable power-down or output enable pin –360.8 –275.9 VPP High voltage for programming NV memory SDATA Serial data pin used for programming in test mode OUT 6 Clock output 360.0 353.7 SCL Serial clock for programm

Summary of the content on the page No. 3

CY2048WAF Output Short Circuit Current..................................... ± 50 mA Absolute Maximum Conditions Storage Temperature (Non-condensing) .... –55°C to +125°C (Above which the useful life may be impaired. Junction Temperature................................ –40°C to +125°C For user guidelines, not tested.) Data Retention @ Tj = 125°C................................> 10 years Supply Voltage (V ) ........................................–0.5 to +7.0V DD ESD (Human Body Model) MIL-STD-883

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CY2048WAF [1] AC Electrical Specifications over the operating range, except as noted [1] Parameter Description Condition Min. Typ. Max. Unit F Output Frequency 0.625 – 48 MHz OUT DC Output Duty Cycle XTAL Buffered or Divided 45 50 55 % T Rise Time Output Clock Rise Time, Measured from 20% to 2.5 ns R 80% of V , C = 15 pF. DD OUT T Fall Time Output Clock Fall Time, Measured from 80% to 2.5 ns F 20% of V , C = 15 pF. DD OUT t RMS Period Jitter XIN = 10–48 MHz. Measured at V /2 – 4 15 ps PJ1 D

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CY2048WAF Timing Parameters over the operating range Parameter Description Min. Max. Unit T Time from falling edge on PD# to stopped output, synchronous mode, T=1/F 1.5T + 350 ns STP,SYNC out T Time from falling edge on PD# to stopped output, asynchronous mode 350 ns STP,ASYNC T Time from rising edge on PD# to output at valid frequency, synchronous mode, 3ms PU,SYNC T=1/F out T Time from rising edge on PD# to output at valid frequency, asynchronous mode 3 ms PU,ASYNC T Time from rising edge on

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CY2048WAF Test and Measurement Set-up VDD Output 0.1 µF C LOAD DUT GND Voltage and Timing Definitions t 1 t 2 V DD 50% of V DD Clock 0V Output Figure 5. Duty Cycle Definition t t F R V DD 80% of V DD 20% of V DD Clock 0V Output Figure 6. Ordering Information Ordering Code Package Type Operating Range (TJ) [3] CY2048WAF Wafer Industrial,–40 °C to 125°C Note: 3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information

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CY2048WAF Document History Page Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Document Number: 38-07738 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 319840 See ECN RGL New data sheet *A 413511 See ECN RGL Minor Change: Pls. post in the web Document #: 38-07738 Rev. *A Page 7 of 7 [+] Feedback