Summary of the content on the page No. 1
PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times The Cypress CY14B101LA/CY14B101NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
■ Internally organized as 128K x 8 (CY14B101LA) or 64K x 16
organized as 128K bytes of 8 bits each or 64K words of 16 bits
(CY14B101NA)
each. The embedded nonvolatile elements incorporate
■ Hands off Automatic STORE on power down with only a
Summary of the content on the page No. 2
CY14B101LA, CY14B101NA PRELIMINARY Pinouts Figure 1. Pin Diagram - 48 FBGA 48-FBGA 48-FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 4 2 3 5 6 1 4 2 3 5 6 A A OE A NC A A A BLE 2 OE NC 0 1 A NC 0 1 2 A DQ A A NC 8 BHE CE DQ B A A 4 NC CE NC B 3 0 3 4 DQ A A DQ DQ C A A C DQ DQ NC NC DQ 9 5 6 1 2 5 10 0 6 4 [4] [5] A V A V DQ V NC V SS DQ 7 CC D SS DQ 7 DQ CC D NC 3 5 11 1 [4] V V V A V CC DQ V DQ SS E DQ V DQ SS E CC 16 12 CAP NC 4 2 CAP 6 A A F A A F DQ DQ DQ DQ NC DQ DQ N
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CY14B101LA, CY14B101NA PRELIMINARY Pinouts (continued) Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC V CAP 1 48 V CC A 16 2 47 A 15 A 14 3 46 HSB A 12 4 45 WE A 7 5 44 A 13 A 6 6 43 A 8 A 5 7 42 A 9 INT 8 41 NC A 4 40 A 9 11 48-SSOP NC 10 39 NC NC 11 38 NC NC Top View 12 37 NC V (not to scale) SS 13 36 V SS NC 14 NC 35 NC 15 NC 34 DQ0 16 33 DQ6 A 3 17 32 OE A 2 18 31 A 10 A 1 19 30 CE A 0 20 29 DQ7 DQ1 21 28 DQ5 DQ2 22 27 DQ4 NC 23 26 DQ3 NC 24 25 V CC Table 1. Pin Definitions Pin Name
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CY14B101LA, CY14B101NA PRELIMINARY Figure 4 shows the proper connection of the storage capacitor Device Operation (V ) for automatic STORE operation. Refer to DC Electrical CAP The CY14B101LA/CY14B101NA nvSRAM is made up of two Characteristics on page 7 for the size of V . The voltage on CAP functional components paired in the same physical cell. They are the V pin is driven to V by a regulator on the chip. Place a CAP CC an SRAM memory cell and a nonvolatile QuantumTrap cell. The pull up on WE
Summary of the content on the page No. 5
CY14B101LA, CY14B101NA PRELIMINARY During any STORE operation, regardless of how it is initiated, The software sequence may be clocked with CE controlled reads the CY14B101LA/CY14B101NA continues to drive the HSB pin or OE controlled reads. After the sixth address in the sequence LOW, releasing it only when the STORE is complete. Upon is entered, the STORE cycle commences and the chip is completion of the STORE operation, the disabled. HSB is driven low. It is important to use read cycles and CY
Summary of the content on the page No. 6
CY14B101LA, CY14B101NA PRELIMINARY Table 2. Mode Selection (continued) [9] [3] A - A Mode I/O Power CE WE OE, BHE, BLE 15 0 [10] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data [10] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0
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CY14B101LA, CY14B101NA PRELIMINARY Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260 °C Storage Temperature ................................. –65 °C to +150 °C DC Output Current (1 output at a time, 1s duration)......15 mA
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CY14B101LA, CY14B101NA PRELIMINARY Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [14] Description Test Conditions Max Unit Parameter C Input Capacitance T = 25 °C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [14] Description Test Conditions 48-FBGA 48-SSOP 44-TSOP II 32-SOIC Unit Parameter Θ Thermal Resistance Test conditions follow standard 28.82 TBD 31.11 T
Summary of the content on the page No. 9
CY14B101LA, CY14B101NA PRELIMINARY AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [15] t Read Cycle Time 20 25 45 ns t RC RC [16] t Address Access Time 20 25 45 ns t AA AA t Output Enable to Data Valid 10 12 20 ns t OE DOE [16] t Output Hold After Address Change 3 3 3 ns t OH OHA [14, 17] t Chip Enable to Output Active 3 3 3 ns t LZ LZCE [14, 17]
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CY14B101LA, CY14B101NA PRELIMINARY [3, 15, 19] Figure 7. SRAM Read Cycle #2: CE and OE Controlled Address Address Valid t t HZCE RC t ACE CE t AA t t LZCE HZOE t DOE OE t t HZBE LZOE t DBE BHE, BLE t LZBE High Impedance Data Output Output Data Valid t PU t PD Active I Standby CC [3, 18, 19, 21] Figure 8. SRAM Write Cycle #1: WE Controlled t WC Address Address Valid t t SCE HA CE t BW BHE, BLE t AW t PWE WE t SA t t SD HD Data Input Input Data Valid t t LZWE HZWE High Impedance Data Output
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CY14B101LA, CY14B101NA PRELIMINARY [3, 18, 19, 21] Figure 9. SRAM Write Cycle #2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t HD SD Data Input Input Data Valid High Impedance Data Output [3, 18, 19, 21] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled t WC Address Address Valid t SCE CE t t t SA HA BW BHE, BLE t AW t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output Document #: 001-42879 Rev. *B Page 11 of 25 [+] Feedbac
Summary of the content on the page No. 12
CY14B101LA, CY14B101NA PRELIMINARY AutoStore/Power Up RECALL 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max [27] Power Up RECALL Duration 20 20 20 ms t HRECALL [23] STORE Cycle Duration 8 8 8 ms t STORE [24] Time Allowed to Complete SRAM Cycle 20 25 25 ns t DELAY Low Voltage Trigger Level 2.65 2.65 2.65 V V SWITCH VCC Rise Time 150 150 150 µs t VCCRISE [14] HSB Output Driver Disable Voltage 1.9 1.9 1.9 V V HDIS t HSB To Output Active Time 5 5 5 µs LZHSB t HSB High Activ
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CY14B101LA, CY14B101NA PRELIMINARY Software Controlled STORE/RECALL Cycle 20 ns 25 ns 45 ns [27, 28] Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL Initiation Cycle Time 20 25 45 ns RC t Address Setup Time 0 0 0 ns SA t Clock Pulse Width 15 20 30 ns CW t Address Hold Time 0 0 0 ns HA t RECALL Duration 200 200 200 µs RECALL Switching Waveforms [28] Figure 12. CE and OE Controlled Software STORE/RECALL Cycle t t RC RC Address Address #1 Address #6 t CW t t SA CW CE t HA t t H
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CY14B101LA, CY14B101NA PRELIMINARY Hardware STORE Cycle 20ns 25ns 45ns Parameters Description Unit Min Max Min Max Min Max t HSB To Output Active Time when write latch not set 20 25 25 ns DHSB t Hardware STORE Pulse Width 15 15 15 ns PHSB [29, 30] t Soft Sequence Processing Time 100 100 100 μs SS Switching Waveforms [23] Figure 14. Hardware STORE Cycle Write latch set t PHSB HSB (IN) t STORE t t HHHD DELAY HSB (OUT) t LZHSB DQ (Data Out) RWI Write latch not set t PHSB HSB pin is driven high
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CY14B101LA, CY14B101NA PRELIMINARY Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations. Table 3. Truth Table for x8 Configuration [2] CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ –DQ ); Read Active 0 7 L H H High Z Output Disabled Active L L X Data in (DQ –DQ ); Write Active 0 7 Table 4. Truth Table for x16 Configuration [2] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby L X X
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CY14B101LA, CY14B101NA PRELIMINARY Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14B101LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS20XC 51-85087 44-pin TSOP II CY14B101LA-BA20XCT 51-85128 48-ball FBGA CY14B101LA-BA20XC 51-85128 48-ball FBGA CY14B101LA-SP20XCT 51-85061 48-pin SSOP CY14B101LA-SP20XC 51-85061 48-pin SSOP CY14B101LA-SZ20XCT 51-85127 32-pin SOIC CY14B101LA-SZ20XC 51-85127 32-pin SOIC CY14B101NA-ZS20XCT 51-85087 44-pin
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CY14B101LA, CY14B101NA PRELIMINARY Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 25 CY14B101LA-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS25XC 51-85087 44-pin TSOP II CY14B101LA-BA25XCT 51-85128 48-ball FBGA CY14B101LA-BA25XC 51-85128 48-ball FBGA CY14B101LA-SP25XCT 51-85061 48-pin SSOP CY14B101LA-SP25XC 51-85061 48-pin SSOP CY14B101LA-SZ25XCT 51-85127 32-pin SOIC CY14B101LA-SZ25XC 51-85127 32-pin SOIC CY14B101NA-ZS25XCT 51-
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CY14B101LA, CY14B101NA PRELIMINARY Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14B101LA-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS45XC 51-85087 44-pin TSOP II CY14B101LA-BA45XCT 51-85128 48-ball FBGA CY14B101LA-BA45XC 51-85128 48-ball FBGA CY14B101LA-SP45XCT 51-85061 48-pin SSOP CY14B101LA-SP45XC 51-85061 48-pin SSOP CY14B101LA-SZ45XCT 51-85127 32-pin SOIC CY14B101LA-SZ45XC 51-85127 32-pin SOIC CY14B101NA-ZS45XCT 51-
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CY14B101LA, CY14B101NA PRELIMINARY Part Numbering Nomenclature CY 14 B 101L A-ZS 20 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) Speed: I - Industrial (–40 to 85°C) Pb-Free 20 - 20 ns 25 - 25 ns Package: 45 - 45 ns BA - 48 FBGA Die revision: ZS - TSOP II Blank: No Rev Data Bus: SP - 48 SSOP st L - x8 A - 1 Rev SZ - 32 SOIC N - x16 Density: 101 - 1 Mb Voltage: B - 3.0V NVSRAM 14 - AutoStore + Software STORE + Hardware STORE Cypress Document #: 001-42879 Re
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CY14B101LA, CY14B101NA PRELIMINARY Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document #: 001-42879 Rev. *B Page 20 of 25 [+] Feedback 1.194 (0.047) 0.991 (0.03
