Summary of the content on the page No. 1
32/40-Bit IEEE Floating-Point
a
DSP Microprocessor
ADSP-21020
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Superscalar IEEE Floating-Point Processor
Off-Chip Harvard Architecture Maximizes Signal INSTRUCTION
DATA ADDRESS
CACHE
GENERATORS JTAG TEST
Processing Performance
PROGRAM & EMULATION
30 ns, 33.3 MIPS Instruction Rate, Single-Cycle DAG 1 DAG 2
SEQUENCER
Execution
100 MFLOPS Peak, 66 MFLOPS Sustained Performance
PROGRAM MEMORY ADDRESS
1024-Point Complex FFT Benchmark: 0.58 ms EXTERNAL
ADDRESS
Divide (y
Summary of the content on the page No. 2
ADSP-21020 Instruction Cache C Source Level Debugger • • The ADSP-21020 includes a high performance instruction A full-featured C source level debugger that works with the cache that enables three-bus operation for fetching an simulator or EZ-ICE emulator to allow debugging of instruction and two data values. The cache is selective—only assembler source, C source, or mixed assembler and C. the instructions whose fetches conflict with program memory Numerical C Compiler • data accesses are cached
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ADSP-21020 CACHE JTAG TEST & MEMORY EMULATION 32 x 48 FLAGS DAG 1 DAG 2 PROGRAM 8 x 4 x 32 8 x 4 x 24 SEQUENCER TIMER 24 PMA BUS PMA DMA BUS 32 DMA 48 PMD BUS PMD BUS CONNECT DMD BUS 40 DMD REGISTER FILE 32-BIT FLOATING-POINT FLOATING & FIXED-POINT 16 x 40 BARREL & FIXED-POINT MULTIPLIER, FIXED-POINT SHIFTER ALU ACCUMULATOR Figure 1. ADSP-21020 Block Diagram the standard IEEE format, whereas the 40-bit IEEE extended- of the ADSP-21020 allow the following nine data transfers to be precision fo
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ADSP-21020 in a specified register, either before (premodify) or after output. The count register is automatically reloaded from a (postmodify) the access. To implement automatic modulo 32-bit period register and the count resumes immediately. addressing for circular buffers, the ADSP-21020 provides buffer System Interface length registers that can be associated with each pointer. Base Figure 2 shows an ADSP-21020 basic system configuration. values for pointers allow circular buffers to be place
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ADSP-21020 1· CLOCK 4 CLKIN RESET IRQ3-0 2 4 SELECTS PMS1-0 DMS3-0 SELECTS OE PMRD DMRD OE PROGRAM DATA WE PMWR DMWR WE MEMORY 24 MEMORY 32 ADDR PMA DMA ADDR 32 48 DMD DATA PMD DATA ADSP-21010 SELECTS PMTS DMTS OE PMPAGE DMPAGE PERIPHERALS WE PMACK DMACK ACK ADDR DATA 5 4 Figure 2. Basic System Configuration The ADSP-21020 also implements on-chip emulation through Pin the JTAG test access port. The processor’s eight sets of break- Name Type Function point range registers enable program execution
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ADSP-21020 Pin Pin Name Type Function Name Type Function DMPAGE O Data Memory Page Boundary. The ADSP- IVDD P Power supply (for internal circuitry), nominally +5 V dc (4 pins). 21020 asserts this pin to signal that a data memory page boundary has been crossed. IGND G Power supply return (for internal circuitry); (7 Memory pages must be defined in the pins). memory control registers. TCK I Test Clock. Provides an asynchronous clock DMTS I/S Data Memory Three-State Control. DMTS for JTAG boundary
Summary of the content on the page No. 7
ADSP-21020 COMPUTE AND MOVE OR MODIFY INSTRUCTIONS 1. compute, DM(Ia, Mb) = dreg1 , PM(Ic, Md) = dreg2 ; | | | | | || | dreg1 = DM(Ia, Mb) dreg2 = PM(Ic, Md) 2. IF condition compute; 3a. IF condition compute, DM(Ia, Mb) = ureg ; | | | | PM(Ic, Md) 3b. IF condition compute, DM(Mb, Ia) = ureg ; | | | | PM(Md, Ic) 3c. IF condition compute, ureg = DM(Ia, Mb) ; | | | | PM(Ic, Md) 3d. IF condition compute, ureg = DM(Mb, Ia) ; | | | | PM(Md, Ic) 4a. IF condition compute, DM(Ia, ) = dreg ; |
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ADSP-21020 IMMEDIATE MOVE INSTRUCTIONS Table II. Condition and Termination Codes 14a. DM() = ureg ; Name Description PM() eq ALU equal to zero 14b. ureg = DM() ; ne ALU not equal to zero PM() ge ALU greater than or equal to zero 15a. DM(, Ia) = ureg; lt ALU less than zero PM(< data24>, Ic) le ALU less than or equal to zero gt ALU greater than zero 15b. ureg = DM(, Ia) ; ac ALU carry PM(, Ic) not ac Not ALU carry 16. DM(Ia, Mb) = ; a
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ADSP-21020 Table III. Universal Registers Table IV. ALU Compute Operations Name Function Fixed-Point Floating-Point Register File Rn = Rx + Ry Fn = Fx + Fy R15–R0 Register file locations Rn = Rx – Ry Fn = Fx – Fy Program Sequencer Rn = Rx + Ry, Rm = Rx – Ry Fn = Fx + Fy, Fm = Fx – Fy PC* Program counter; address of instruction cur- Rn = Rx + Ry + CI Fn = ABS (Fx + Fy) rently executing Rn = Rx – Ry + CI – l Fn = ABS (Fx – Fy) PCSTK Top of PC stack Rn = (Rx + Ry)/2 Fn = (Fx + Fy)/2 PCSTKP PC stack
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ADSP-21020 Table V. Multiplier Compute Operations Rn = Rx * Ry (SS F ) Fn = Fx * Fy MRF = Rx * Ry (UU I MRB = Rx * Ry (U U FR Rn = MRF + Rx * Ry (SS F ) Rn = MRF – Rx * Ry (SS F ) Rn = MRB + Rx * Ry (UU I Rn = MRB= Rx * Ry ( UUI MRF = MRF + Rx * Ry ( U U FR MRF = MRF= Rx * Ry (UU I FR MRB = MRB MRB = MRB Rn = SAT MRF (SI) Rn = RND MRF (SF) Rn = SAT MRB (UI) Rn = RND MRB (UF) MRF = SAT MRF (SF) MRF = RND MRF MRB = SAT MRB (UF) MRB = RND MRB MRF = 0 MRB MRxF = Rn Rn = MRxF MRxB Rn = MRxB Rn, Rx, R
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ADSP-21020 Table Vll. Multifunction Compute Operations Table VIII. Interrupt Vector Addresses and Priorities Fixed-Point Vector Address Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 No. (Hex) Function Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 0 0x00 Reserved MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 1* 0x08 Reset MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12 2 0xl0 Reserved MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 3 0xl8 Status stack or loop
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ADSP-21020–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade T Grade Parameter Min Max Min Max Min Max Unit V Supply Voltage 4.50 5.50 4.50 5.50 4.50 5.50 V DD T Ambient Operating Temperature 0 +70 –40 +85 –55 +125 °C AMB Refer to Environmental Conditions for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min Max Unit 1 V Hi-Level Input Voltage V = max 2.0 V IH DD 2, 12 V Hi-Level Input Voltage V = max 3.0 V IHCR DD 1, 12 V L
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ADSP-21020 TIMING PARAMETERS General Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive other specifications. Clock Signal K/B/T Grade K
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ADSP-21020 Interrupts K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t IRQ3-0 Setup before CLKIN High 38 31 25 23 38 + 3DT/4 ns SIR t IRQ3-0 Hold after CLKIN High 0 0 0 0 ns HIR t IRQ3-0 Pulse Width 55 45 38 35 t + 5 ns IPW CK NOTE *DT = t – 50 ns CK Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the se
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ADSP-21020 Flags K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit 1 Timing Requirement: t FLAG3-0 Setup before CLKIN High 19 16 14 13 19 + 5DT/16 ns SFI IN t FLAG3-0 Hold after CLKIN High 0 0 0 0 ns HFI IN t FLAG3-0 Delay from xRD, xWR Low 12 8 5 3 12 + 7DT/16 ns DWRFI IN t FLAG3-0 Hold after xRD, xWR00 0 0 ns HFIWR IN Deasserted Switching Characteristic: t FLAG3-0 Delay from CLKIN High 24 24 24 2
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ADSP-21020 Bus Request/Bus Grant K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t BR Hold after CLKIN High 0 0 0 0 ns HBR t BR Setup before CLKIN High 18 15 13 12 18 + 5DT/16 ns SBR Switching Characteristic: t Memory Interface Disable to BG Low –2 –2 –2 –2 ns DMDBGL t CLKIN High to Memory Interface DME Enable 25 20 16 15 25 + DT/2 ns t CLKIN High to BG Low 22 22 22 22 ns DBGL
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ADSP-21020 External Memory Three-State Control K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t xTS, Setup before CLKIN High 14 50 12 40 10 33 9 30 14 + DT/4 t ns STS CK t xTS Delay after Address, Select 28 19 13 10 28 + 7DT/8 ns DADTS t xTS Delay after XRD, XWR Low 16 11 7 6 16 + DT/2 ns DSTS Switching Characteristic: t Memory Interface Disable before DTSD CLKIN High 0 –2 –4
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ADSP-21020 Memory Read K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t Address, Select to Data Valid 37 27 20 17 37 + DT ns DAD t xRD Low to Data Valid 24 18 13 11 24 + 5DT/8 ns DRLD t Data Hold from Address, Select 0 0 0 0 ns HDA t Data Hold from xRD High –1 –1 –1 –1 ns HDRH t xACK Delay from Address 27 18 12 9 27 + 7DT/8 ns DAAK t xACK Delay from xRD Low 15 10 6 5 15 + DT/
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ADSP-21020 CLKIN ADDRESS, SELECT t DAP DMPAGE, PMPAGE t DCKRL t t DARL RW DMRD, PMRD t HDA t DRLD t HDRH t DAD DATA t t DRAK RWR t t t SAK DAAK HAK DMACK, PMACK DMWR, PMWR Figure 10. Memory Read REV. C –19–
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ADSP-21020 Memory Write K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: 12 t xACK Delay from Address, Select 27 18 6 9 27 + 7DT/8 ns DAAK t xACK Delay from xWR Low 15 10 10 5 15 + DT/2 ns DWAK t xACK Setup before CLKIN High 14 12 0 9 14 + DT/4 ns SAK t xACK Hold after CLKIN High 0 0 0 ns HAK Switching Characteristic: t Address, Select to xWR Deasserted 37 28 21 18 37+ 15DT/16
