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ANY-FREQUENCY PRECISION CLOCKS
Si5316, Si5319, Si5322, Si5323, Si5324, Si5325,
Si5326, Si5327, Si5365, Si5366, Si5367,
Si5368, Si5369, Si5374, Si5375
FAMILY REFERENCE MANUAL
Rev. 0.5 6/11 Copyright © 2011 by Silicon Laboratories Si53xx-RM
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Si53xx-RM 2 Rev. 0.5
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Si53xx-RM TABLE OF CONTENTS Section Page 1. Any-Frequency Precision Clock Product Family Overview . . . . . . . . . . . . . . . . . . . . . .12 2. Narrowband vs. Wideband Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3. Any-Frequency Clock Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1. Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM 6.3.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4. Digital Hold/VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM and Si5375 Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.5.1. Free Run Mode Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.2. Clock Control Logic in Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.3. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM 8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369) . . . . . . 107 8.2.2. Typical Output Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2.3. Typical Clock Output Scope Shots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.3. Typical Scope Shots for SFOUT Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
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Si53xx-RM LIST OF FIGURES Figure 1. Si5316 Any-Frequency Jitter Attenuator Block Diagram . . . . . . . . . . . . . . . . . . . . . 17 Figure 2. Si5319 Any-Frequency Jitter Attenuating Clock Multiplier Block Diagram . . . . . . . .18 Figure 3. Si5322 Low Jitter Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Si5323 Jitter Attenuating Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . 20 Figure 5. Si5324 Clock Multiplier and J
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Si53xx-RM Figure 43. Differential Output Example Requiring Attenuation . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together). . . . . . . 108 Figure 45. CKOUT Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 46. sfout_2, CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 47. sfout_3, lowSwi
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Si53xx-RM Figure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) . . . . . . . . . . . . . . . . . .165 Figure 89. RF Generator, Si5326, Si5324 (50 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 90. RF Generator, Si5326, Si5324 (100 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 91. RF Generator, Si5326, Si5324 (500 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 92. RF Generator, Si5326, Si53
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Si53xx-RM LIST OF TABLES Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. Product Selection Guide (Si5322/25/65/67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 Table 3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 4. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM Table 42. Digital Hold History Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 43. Digital Hold History Averaging Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) . . . . . . . . . . . . . . . . . . . . . . . 92 Table 45. Common NC5 Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 46. A
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Si53xx-RM 1. Any-Frequency Precision Clock Product Family Overview Silicon Laboratories Any-Frequency Precision Clock products provide jitter attenuation and clock multiplication/ clock division for applications requiring sub 1 ps rms jitter performance. The device product family is based on Silicon Laboratories' 3rd generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for discrete VCXO/VCSOs and
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Si53xx-RM A wide range of settings are available, but they are a subset of the frequency plans supported by the Si5323 and Si5366 jitter-attenuating clock multipliers. The Si5325 and Si5367 are microprocessor-controlled clock multipliers 2 that can be controlled via an I C or SPI interface. These devices accept clock inputs ranging from 10MHz to 710MHz and generate multiple independent, synchronous clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 and Si
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Si53xx-RM Table 1. Product Selection Guide Part Control Number of Input Output RMS Phase Jitter PLL Hitless Free Package Number Inputs and Frequency Frequency (12kHz–20MHz) Bandwidth Switching Run * * Outputs Mode (MHz) (MHz) 60 Hz to 6x6 mm Si5315 Pin 1PLL, 2 | 2 0.008–644 0.008–644 0.45 ps 8kHz 36-QFN 60 Hz to 6x6 mm Si5316 Pin 1PLL, 2 | 1 19–710 19–710 0.3 ps 8kHz 36-QFN 60 Hz to 6x6 mm Si5317 Pin 1PLL, 1 | 2 1–710 1–710 0.3 ps 8kHz 36-QFN 60 Hz to 6x6 mm 2 Si5319 I C/SPI 1PLL, 1 | 1 0.002
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Si53xx-RM Table 2. Product Selection Guide (Si5322/25/65/67) Low Jitter Precision Clock Multipliers (Wideband) Si5322 2 2 707 1050 0.6 ps rms typ Si5325 2 2 710 1400 0.6 ps rms typ Si5365 4 5 707 1050 0.6 ps rms typ Si5367 4 5 710 1400 0.6 ps rms typ Notes: 1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering information. 2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal o
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Si53xx-RM 2. Narrowband vs. Wideband Overview The narrowband (NB) devices offer a number of features and capabilities that are not available with the wideband (WB) devices, as outlined in the below list: Broader set of frequency plans due to more divisor options Hitless switching between input clocks Lower minimum input clock frequency Lower loop bandwidth Digital Hold (reference-based holdover instead of VCO freeze) FRAMESYNC realignment CLAT and FLAT (input to output skew adjust
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Si53xx-RM 3. Any-Frequency Clock Family Members 3.1. Si5316 The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC- 192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 14% higher than nominal SONET/SDH frequencies
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Si53xx-RM 3.2. Si5319 The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si53
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Si53xx-RM 3.3. Si5322 The Si5322 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency- multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI) rates. The DSPLL loop bandwi
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Si53xx-RM 3.4. Si5323 The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI). The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and
