Summary of the content on the page No. 1
Video Coprocessor
CYV15G0404DXB
Independent Clock Quad HOTLink II™
Transceiver with Reclocker
■ Synchronous LVTTL parallel interface
Features
■ JTAG boundary scan
■ Quad channel transceiver for 195 to 1500 MBaud serial
signaling rate
■ Built In Self Test (BIST) for at-speed link testing
❐ Aggregate throughput of up to 12 Gbits/second
■ Link quality indicator by channel
®
■ Second-generation HOTLink technology
❐ Analog signal detect
❐ Digital signal detect
■ Compliant to multiple standards
❐ SMP
Summary of the content on the page No. 2
CYV15G0404DXB The CYV15G0404DXB satisfies the SMPTE-259M and 8B/10B decoded, and checked for transmission errors. SMPTE-292M compliance according to SMPTE EG34-1999 Recovered decoded characters are then written to an internal Pathological Test Requirements. elasticity buffer, and presented to the destination host system. As a second generation HOTLink device, the CYV15G0404DXB The integrated 8B/10B encoder or decoder may be bypassed for extends the HOTLink family with enhanced levels of integra
Summary of the content on the page No. 3
CYV15G0404DXB RECLCK[A..D] are Internal Reclocker Signals Transmit Path Block Diagram TXLB[A..D] are Internal Serial Loopback Signals REFCLKA+ Bit-Rate Clock REFCLKA– = Internal Signal Tr Tans ransmit PLL mit PLL OEA[2..1] TXRATEA Clock Mul Clock Multipli tiplier er A SPDSELA ENCBYPA TXCLKOA Character-Rate Clock A RECLCKA TXERRA OEA[2..1] TXBISTA PABRSTA TXCLKA 0 1 TXCKSELA 8 OUTA1+ TXDA[7:0] 10 10 OUTA1– 10 10 2 OUTA2+ TXCTA[1:0] OUTA2– TXLBA REFCLKB+ Bit-Rate Clock REFCLKB– Transmit PLL TXRAT
Summary of the content on the page No. 4
CYV15G0404DXB RECLCK[A..D] are Internal Reclocker Signals Receive Path Block = Internal Signal TXLB[A..D] are Internal Serial Loopback Signals RESET TRST JTAG TMS SPDSELA Boundary TCLK RXPLLPDA Scan RCLKENA TDI RECLCKA Controller TDO Receive LPENA Signal INSELA LFIA Monitor INA1+ INA1– 8 RXDA[7:0] INA2+ Clock & INA2– Data TXLBA Recovery 3 RXSTA[2:0] PLL ULCA SPDSELB RXPLLPDB Clock RXCLKA+ RECLCKB ÷2 RCLKENB Select RXCLKA– Receive LPENB LFIB Signal INSELB Monitor INB1+ INB1– 8 RXDB[7:0] INB2+ C
Summary of the content on the page No. 5
CYV15G0404DXB Device Configuration and Control Block = Internal Signal RFMODE[A..D][1:0] RFEN[A..D] FRAMCHAR[A..D] WREN DECMODE[A..D] Device Configura- RXBIST[A..D] ADDR[3:0] tion and Control RXCKSEL[A..D] DATA[7:0] DECBYP[A..D] Interface RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D] TXRATE[A..D] TXCKSEL[A..D] PABRST[A..D] TXBIST[A..D] OE[A..D][2..1] ENCBYP[A..D] GLEN[11..0] FLEN[2..0] Document #: 38-02097 Rev. *B Page 5 of 44 [+] Feedback [+] Feedback
Summary of the content on the page No. 6
CYV15G0404DXB Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT V GND GND V CC CC C1– C1– C2– C2– D1– D1– D2– D2– A1– A1– A2– A2– B1– B1– B2– B2– B IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT V GND GND V CC CC C1+ C1+ C2+ C2+ D1+ D1+ D2+ D2+ A1+ A1+ A2+ A2+ B1+ B1+ B2+ B2+ C TDI TMS INSELC INSELB ULCD ULCC DATA DATA DATA DATA RCLK SPD LDTD TRST LPEND TDO V GND GND V CC CC [7] [5] [3] [1] ENB SELD
Summary of the content on the page No. 7
CYV15G0404DXB Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN V GND GND V CC CC A B2– B2– B1– B1– A2– A2– A1– A1– D2– D2– D1– D1– C2– C2– C1– C1– OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN V GND GND V CC CC B B2+ B2+ B1+ B1+ A2+ A2+ A1+ A1+ D2+ D2+ D1+ D1+ C2+ 2+ C1+ C1+ TDO LP TRST LDTD SPD RCLK DATA DATA DATA DATA ULCC ULCD IN IN TMS TDI V GND GND V CC CC C END EN SELD ENB [1] [3] [5] [7] SE
Summary of the content on the page No. 8
CYV15G0404DXB Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDA[7:0] LVTTL Input, Transmit Data Inputs. TXDx[7:0] data inputs are captured on the rising edge of the TXDB[7:0] synchronous, transmit interface clock. The transmit interface clock is selected by the TXCKSELx TXDC[7:0] sampled by the latch via the device configuration interface, and passed to the encoder or Transmit TXDD[7:0] associated Shif
Summary of the content on the page No. 9
CYV15G0404DXB Pin Definitions (continued) CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description TXCLKOA LVTTL Output Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s TXCLKOB transmit PLL and operates synchronous to the internal transmit character clock. TXCLKOC TXCLKOx operates at either the same frequency as REFCLKx± (TXRATE = 0), or at TXCLKOD twice the frequency of REFCLKx± (TXRATE = 1). The transmit clock outputs have no fixed phase
Summary of the content on the page No. 10
CYV15G0404DXB Pin Definitions (continued) CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description LDTDEN LVTTL Input, Level Detect Transition Density Enable. When LDTDEN is HIGH, the signal level internal pull up detector, range controller, and transition density detector are all enabled to determine if the RXPLL tracks REFCLKx± or the selected input serial data stream. If the signal level detector, range controller, or transition density detector are out of their r
Summary of the content on the page No. 11
CYV15G0404DXB Pin Definitions (continued) CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description LFIA LVTTL Output, Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the LFIB asynchronous logical OR of five internal conditions. LFIx is asserted LOW when any of these condi- LFIC tions are true: LFID ■ Received serial data rate outside expected range ■ Analog amplitude below expected levels ■ Transition density lower than expected ■ Re
Summary of the content on the page No. 12
CYV15G0404DXB Pin Definitions (continued) CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description Factory Test Modes SCANEN2 LVTTL input, Factory Test 2. SCANEN2 input is for factory testing only. Leave this input as a NO internal pull down CONNECT or GND only. TMEN3 LVTTL input, Factory Test 3. TMEN3 input is for factory testing only. Leave this input as a NO internal pull down CONNECT or GND only. Analog I/O OUTA1± CML Differential Primary Differential Serial Da
Summary of the content on the page No. 13
CYV15G0404DXB Once initialized, TXCLKx is allowed to drift in phase as much as Depending on the operational mode, the generated transmission ±180 degrees. If the input phase of TXCLKx drifts beyond the character may be handling capacity of the phase align buffer, TXERRx is asserted ■ The 10-bit preencoded character accepted in the input register. to indicate the loss of data, and remains asserted until the phase align buffer is initialized. The phase of the TXCLKx relative to its ■ The 10-bit eq
Summary of the content on the page No. 14
CYV15G0404DXB sequence. At the end of this sequence, if the TXCTx[1:0] = 11 Transmit Modes condition is sampled again, the sequence restarts and remains Encoder Bypass uninterruptible for the following 15 character clocks. When the Encoder is bypassed, the character captured from the Transmit BIST TXDx[7:0] and TXCTx[1:0] input register is passed directly to the transmit shifter without modification. With the encoder bypassed, Each transmit channel contains an internal pattern generator that the
Summary of the content on the page No. 15
CYV15G0404DXB The REFCLKx± inputs are differential inputs with each input The local internal loopback (LPENx) allows the serial transmit internally biased to 1.4V. If the REFCLKx+ input is connected to data outputs to be routed internally back to the clock and data a TTL, LVTTL, or LVCMOS clock source, the input signal is recovery circuit associated with each channel. When configured recognized when it passes through the internally biased for local loopback, the associated transmit serial driver
Summary of the content on the page No. 16
CYV15G0404DXB Transition Density Each CDR accepts a character rate (bit-rate ÷10) or half-character rate (bit-rate ÷ 20) reference clock from the The transition detection logic checks for the absence of transi- associated REFCLKx± input. This REFCLKx± input is used to tions spanning greater than six transmission characters (60 bits). If no transitions are present in the data received, the detection ■ Ensure that the VCO (within the CDR) is operating at the correct logic for that channel asserts
Summary of the content on the page No. 17
CYV15G0404DXB through the FRAMCHARx latches through the configuration characters, received as consecutive characters, on identical interface. 10-bit boundaries, before character framing is adjusted. The specific bit combinations of these framing characters are 10B/8B Decoder Block listed in Table 6. When the specific bit combination of the The decoder logic block performs two primary functions: selected framing character is detected by the framer, the bound- aries of the characters present in t
Summary of the content on the page No. 18
CYV15G0404DXB Code rule violations or running disparity errors that occur as part RXRATEx) and delayed form of REFCLKx±. In this mode, the of the BIST loop do not cause an error indication. RXSTx[2:0] receive elasticity buffers are enabled. For REFCLKx± clocking, indicates 010b or 100b for one character period per BIST loop to the elasticity buffers must be able to insert K28.5 characters and indicate loop completion. This status can be used to check test delete framing characters as appropriate
Summary of the content on the page No. 19
CYV15G0404DXB This adjustment only occurs when the framer is enabled. When Table 7. Output Register Bit Assignments the framer is disabled, the clock boundaries are not adjusted, BYPASS ACTIVE DECODER and COMDETx may be asserted during the rising edge of Signal Name (DECBYPx = 0) (DECBYP = 1) RXCLKx– (if an odd number of characters were received following the initial framing). RXSTx[2] (LSB) COMDETx RXSTx[2] RXSTx[1] DOUTx[0] RXSTx[1] Receive Status Bits RXSTx[0] DOUTx[1] RXSTx[0] When the 1
Summary of the content on the page No. 20
CYV15G0404DXB 12, 13, and 14 consist of global configuration bits and the last basis. A logic 1 in a bit location allows for the update of that same latch bank (15) is the mask latch bank that can be configured to location of the target latch bank(s), whereas a logic 0 disables it. perform bit-by-bit configuration. The reset value of this latch bank is FFh, thereby making its use optional by default. The mask latch bank is not maskable. The Global Enable Function FGLEN functionality is not affec
