Summary of the content on the page No. 1
NI 5421 Specifications
NI PXI/PCI-5421 16-Bit 100 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Analog Filter enabled.
Interpolation set to maximum allowed factor for a given sample rate.
Signals terminated with 50 Ω .
Direct Path set to 1 V , Low-Gain Amplifier Path set to 2 V ,
pk-pk pk-pk
and High-Gain Amplifier Path set to 12 V .
pk-pk
Sample clock set to 100 MS/s.
Typical values are representative of an avera
Summary of the content on the page No. 2
CH 0 (Channel 0 Analog Output, Front Panel Connector) Table 1. Specification Value Comments Number of 1 — Channels Connector SMB (jack) — Output Voltage Characteristics Output Paths 1. The software-selectable Main Output Path setting — provides full-scale voltages from 12.00 V to pk-pk 5.64 mV into a 50 Ω load. NI-FGEN uses either the pk-pk Low-Gain Amplifier or the High-Gain Amplifier when the Main Output Path is selected, depending on the Gain attribute. 2. The software-selectable Direct
Summary of the content on the page No. 3
Table 1. (Continued) Specification Value Comments Amplitude and Offset Amplitude Amplitude (V ) 1. Amplitude pk-pk Range values assume Path Load Minimum Value Maximum Value the full scale of the DAC is Direct 50 Ω 0.707 1.00 utilized. If an 1 kΩ 1.35 1.91 amplitude smaller than Open 1.41 2.00 the minimum value is Low- 50 Ω 0.00564 2.00 desired, then Gain waveforms less 1 kΩ 0.0107 3.81 Amplifier than full scale of the DAC can Open 0.0113 4.00 be used. High- 50 Ω 0.0338 12.0 2. NI
Summary of the content on the page No. 4
Table 1. (Continued) Specification Value Comments Maximum Output Voltage Maximum Path Load Maximum Output Voltage (V ) The Maximum pk-pk Output Output Voltage Direct 50 Ω ±0.500 Voltage of the NI 5421 is determined by 1 kΩ ±0.953 the Amplitude Range and the Open ±1.000 Offset Range. Low- 50 Ω ±1.000 Gain 1 kΩ ±1.905 Amplifier Open ±2.000 High- 50 Ω ±6.000 Gain 1 kΩ ±11.43 Amplifier Open ±12.00 Accuracy DC Accuracy For the Low-Gain or High-Gain Amplifier Path: All paths are calibrated
Summary of the content on the page No. 5
Table 1. (Continued) Specification Value Comments Output DC — Coupling Output Software-selectable. When disabled, CH 0 out is terminated — Enable with a 1 W resistor with a value equal to the selected output impedance. Maximum The CH 0 output can be connected to a 50 Ω , ±12 V — Output (±8 V for the Direct Path) source without sustaining any Overload damage. No damage occurs if the CH 0 output is shorted to ground indefinitely. Waveform The CH 0 output supports waveform summing among — Summ
Summary of the content on the page No. 6
2.0 +0.6 dB 1.0 +0.4 dB +0.3 dB 0.0 –1.0 –0.4 dB –0.4 dB –0.4 dB –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 Guaranteed Specification –8.0 Typical –9.0 –10.0 1.0M 10.0M 48.0M Frequency (Hz) Figure 1. Normalized Passband Flatness, Direct Path 2.0 1.6 1.2 0.8 0.4 0.0 –0.4 –0.8 –1.2 –1.6 –2.0 0.0 20.0n 40.0n 60.0n 80.0n 100.0n Time (s) Figure 2. Pulse Response, Low-Gain Amplifier Path 50 Ω Load NI 5421 Specifications 6 ni.com Amplitude (V) dB
Summary of the content on the page No. 7
Table 1. (Continued) Specification Value Comments Suggested Maximum Frequencies for Common Functions Function Path Disable the Analog Filter Low-Gain High-Gain and the Digital Direct Amplifier Amplifier Interpolation Filter for Square, Sine 43 MHz 43 MHz 43 MHz Ramp, and Square Not Recommended 25 MHz 12.5 MHz Triangle. Ramp Not Recommended 5 MHz 5 MHz Triangle Not Recommended 5 MHz 5 MHz Spectral Characteristics Signal to Path Amplitude Noise and –1 dBFS. Distortion Low-Gain High-Ga
Summary of the content on the page No. 8
Table 1. (Continued) Specification Value Comments Spectral Characteristics (Continued) Spurious-Free Path Amplitude Dynamic –1 dBFS. Range Measured from (SFDR) with Low-Gain High-Gain DC to 50 MHz. Harmonics Direct Amplifier Amplifier Also called harmonic 1 MHz –76 dBc –71 dBc –58 dBc distortion. SFDR with 10 MHz –68 dBc –64 dBc –47 dBc harmonics at low 20 MHz –60 dBc –57 dBc –42 dBc amplitudes is limited by a 30 MHz –73 dBc –73 dBc –74 dBc –148 dBm/Hz 40 MHz –76 dBc –73 dBc –74 dBc no
Summary of the content on the page No. 9
Table 1. (Continued) Specification Value Comments Spectral Characteristics (Continued) 0 ºC to 40 ºC Path Amplitude Total –1 dBFS. nd Harmonic Includes the 2 th Distortion Low-Gain High-Gain through the 6 (THD) Direct Amplifier Amplifier harmonic. –77 dBc 20 kHz –77 dBc (typical) (typical) –77 dBc (typical) –70 dBc 1 MHz –75 dBc (typical) (typical) –62 dBc (typical) 5 MHz –68 dBc –68 dBc –55 dBc 10 MHz –65 dBc –61 dBc –46 dBc 20 MHz –55 dBc –53 dBc — 30 MHz –50 dBc –48 dBc — 40 MHz –48 dB
Summary of the content on the page No. 10
Table 1. (Continued) Specification Value Comments Average Noise Amplitude Average Noise Density Range Average Noise Density Density at small amplitudes is nV dBFS/ - ---- ---- - - limited by a Path V dBm dBm/Hz Hz Hz pk-pk –148 dBm/Hz noise floor. Direct 1 4.0 18 –142 –146.0 Low Gain 0.06 –20.4 9 –148 –127.6 Low Gain 0.1 –16.0 9 –148 –132.0 Low Gain 0.4 –4.0 13 –145 –141.0 Low Gain 1 4.0 18 –142 –146.0 Low Gain 2 10.0 35 –136 –146.0 High Gain 4 16.0 71 –130 –146.0 High Gain 12 25.6 213 –12
Summary of the content on the page No. 11
10.0 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 25.0M 50.0M 75.0M 100.0M 125.0M 158.0M 175.0M 200.0M Frequency (Hz) Figure 3. 10 MHz Single-Tone Spectrum, Direct Path, 100 MS/s, Interpolation Factor Set to 4 Note The noise floor in Figure 3 is limited by the measurement device. Refer to the Average Noise Density specification. © National Instruments Corporation 11 NI 5421 Specifications dBm
Summary of the content on the page No. 12
20.0 10.0 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 25.0M 50.0M 75.0M 100.0M 125.0M 150.0M 175.0M 200.0M Frequency (Hz) Figure 4. 10 MHz Single-Tone Spectrum, Low-Gain Amplifier Path, 100 MS/s, Interpolation Factor Set to 4 Note The noise floor in Figure 4 is limited by the measurement device. Refer to the Average Noise Density specification. NI 5421 Specifications 12 ni.com dBm
Summary of the content on the page No. 13
10.0 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 25.0M 50.0M 75.0M 100.0M 125.0M 150.0M 175.0M 200.0M Frequency (Hz) Figure 5. Direct Path, 2-Tone Spectrum (Typical) Note The noise floor in Figure 5 is limited by the measurement device. Refer to the Average Noise Density specification. © National Instruments Corporation 13 NI 5421 Specifications dBm
Summary of the content on the page No. 14
Sample Clock Table 2. Specification Value Comments Sources 1. Internal, Divide-by-N (N ≥ 1) Refer to the Onboard Clock 2. Internal, DDS-based, High-Resolution section for more 3. External, CLK IN (SMB front panel connector) information about Internal 4. External, DDC CLK IN (DIGITAL DATA & Clock Sources. CONTROL front panel connector) 5. NI PXI-5421: External, PXI Star trigger (backplane connector) 6. NI PXI-5421: External, PXI_Trig<0..7> (backplane connector) NI PCI-5421: External, RT
Summary of the content on the page No. 15
Table 2. (Continued) Specification Value Comments Effective Sample Rate Sample Rate Interpolation Effective Sample Effective Sample (MS/s) Factor Rate Rate = (Interpolation 10 S/s to 1 (Off) 10 S/s to Factor) * (Sample 105 MS/s 105 MS/s Rate) 12.5 MS/s to 2 25 MS/s to 105 MS/s 210 MS/s 10 MS/s to 4 40 MS/s to 100 MS/s 400 MS/s 10 MS/s to 8 80 MS/s to 50 MS/s 400 MS/s Sample Clock Delay Range and Resolution Sample Clock Delay Adjustment Delay Adjustment — Source Range Resolution Divide-
Summary of the content on the page No. 16
Table 2. (Continued) Specification Value Comments System Phase Noise and Jitter (10 MHz Carrier) Sample Clock System Phase Noise 1. High- Source Density Resolution System Output Jitter (dBc/Hz) Offset specifications (Integrated from increase as the 100 Hz 1 kHz 10 kHz 100 Hz to 100 kHz) Sample Rate is decreased. NI PXI-5421 –107 –121 –137 <1.2 ps rms Divide-by-N 2. NI PXI-5421 PXI Star NI PCI-5421 –110 –127 –137 <2.0 ps rms trigger Divide-by-N specification is High- –109 –121 –123 <4.
Summary of the content on the page No. 17
Table 2. (Continued) Specification Value Comments Sample Clock Exporting Exported 1. PFI<0..1> (SMB front panel connectors) Exported Sample Sample Clock Clocks can be 2. DDC CLK OUT (DIGITAL DATA & CONTROL front Destinations divided by integer panel connector) K (1 ≤ K ≤ 3. NI PXI-5421—PXI_Trig<0..7> (backplane connector) 4,194,304). NI PCI-5421—RTSI<0..7> Exported — Sample Clock Maximum Destinations Frequency Jitter (Typical) Duty Cycle PFI<0..1> 105 MHz PFI 0: 6 ps rms 25% to 65% PFI 1
Summary of the content on the page No. 18
Phase-Locked Loop (PLL) Reference Clock Table 4. Specification Value Comments Sources 1. NI PXI-5421—PXI_CLK10 (backplane connector) The PLL NI PCI-5421—RTSI_7 (RTSI_CLK) Reference Clock provides the 2. CLK IN (SMB front panel connector) reference frequency for the phase-locked loop. Frequency When using the PLL, the Frequency Accuracy of the — Accuracy NI 5421 is solely dependent on the Frequency Accuracy of the PLL Reference Clock Source. Lock Time Typical: 70 ms. — Maximum: 200 ms. F
Summary of the content on the page No. 19
CLK IN (Sample Clock and Reference Clock Input, Front Panel Connector) Table 5. Specification Value Comments Connector SMB (jack) — Direction Input — Destinations 1. Sample Clock — 2. PLL Reference Clock Frequency 1 MHz to 105 MHz (Sample Clock destination and — Range sine waves) 200 kHz to 105 MHz (Sample Clock destination and square waves) 5 MHz to 20 MHz (PLL Reference Clock destination) Input Voltage Sine wave: 0.65 V to 2.8 V into 50 Ω — pk-pk pk-pk Range (0 dBm to +13 dBm) Square wave:
Summary of the content on the page No. 20
PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors) Table 6. Specification Value Comments Connectors Two SMB (jack) — Direction Bi-directional — Frequency DC to 105 MHz — Range As an Input (Trigger) Destinations Start Trigger — Maximum –2 V to +7 V — Input Overload V 2.0 V IH V 0.8 V IL Input 1 kΩ Impedance As an Output (Event) Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304) — 2. Sample Clock Timebase (100 MHz) divided by integer M (2 ≤ M ≤ 4,194,304) 3.
