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Freescale Semiconductor, Inc.
¨
MICROPROCESSORS
THE MOTOROLA GATEWAY BOARD
(MCF5202 Microprocessor To MC68EC000 Bus Interface Card)
Jeff Miller
October 15, 1997
1.0 Introduction
The integrated Gateway circuit board will bridge an existing MC68EC000 system to the new ColdFire¨
MCF5202 VL-RISC microprocessor, to evaluate the possibility of moving toward a higher performance architecture.
It can be used to evaluate system enhancements such as on-chip instruction and/or data cac
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Freescale Semiconductor, Inc. 2.1.1 Mapping 32-bit MCF5202 addresses to 24-bit 68EC000 addresses The Gateway board transfers only the lower 24-bits of the address from the MCF5202 to the MC68EC000. This should make no difference in porting the system software (because a 24-bit addressing scheme can still be used, with the upper 8-bits as a ÒdonÕt-careÒ) except when the on-chip cache is to be used. The MCF5202 allows speciÞc regions of address space to be assigned access c
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Freescale Semiconductor, Inc. cache mode to cache-inhibit. This will require the microprocessor to go to external memory to get accurate data as opposed to having a cache hit within internal memory which could possibly contain stale data. 2.1.3 RMW cycles If the TAS instruction is used in the original M68000 code for implementing the locked or read-modify-write transfer sequence in hardware, then new code will have to be written that essentially implements the same locked tran
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Freescale Semiconductor, Inc. Table 2: Bus Clock Timing Comparison (16-bit mode) READ/ GATEWAY BOARD EQUIVALENT MC68EC000 BUS MCF5202 DATA ACCESS WRITE BUS CLOCKS CLOCKS TO GET SAME DATA Byte, Word Read 7 4 Long 6+7=13 4+4=8 Byte, Word Write 7 4 Long 5+7=12 4+4=8 Line Fill (4 Longs) Read 6+6+6+6+6+6+6+7=49 4+4+4+4+4+4+4+4=32 Line Fill (4 Longs) Write 5+5+5+5+5+5+5+7=42 4+4+4+4+4+4+4+4=32 Table 3: Bus Clock Timing Comparison (8-bit mode) READ/ GATEWAY BOARD EQUIVALENT MC68EC000 BU
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Freescale Semiconductor, Inc. Table 4: Dhrystone 2.1 Benchmark Performance MIPS DATA DRAM ACCESSES CACHE SYSTEM FREQUENCY (@ GIVEN WIDTH (TO GET 16 BYTES) MODE FREQUENCY) MC68EC000 Board 16 bit 12.5 MHz 8-8-8-8-8-8-8-8 N/A 1.01 Gateway Board 8 bit 20 MHz R: 10-10-10-11-10-10-10-11- Off 0.56 10-10-10-11-10-10-10-11 W: 9- 9- 9-11- 9- 9- 9-11- 9- 9- 9-11- 9- 9- 9-11 Gateway Board 16 bit 20 MHz R: 10-11-10-11-10-11-10-11 Off 1.07 W: 9-11- 9-11- 9-11- 9-11 Gateway Board 8 bi
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Freescale Semiconductor, Inc. 6.0 Bus Operation The Gateway board supports a synchronous interface between the MCF5202 bus and the MC68EC000 bus. The waveforms in this document are meant to provide a functional description of the bus cycles required for data transfer operations. The examples below show a longword read and write to a 16-bit wide data bus of the MC68EC000 as well as an Interrupt Acknowledge Cycle. Note that at all times the MCF5202 will not burst (TBI*=0) and tha
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Freescale Semiconductor, Inc. Figure 2: Longword Write To A 16-Bit Port PS1 PS1 PS2 PS3 PS4 PS5 PS1 PS2 PS3 PS4 PS5 PS1 PS1 PS1 w w S0 S2S4S6 w S0 S2 S4 S6 w w w CLOCK TS* R/W* 00 TT[1:0] ATM SIZ[1:0] 00 10 ADDR WRITE D[31:16] ADDR WRITE D[15:0] AD[31:16] ADDR ADDR AD[15:0] 01 01 DA*[1:0] FC[2:0] A[23:0] AS* UDS LDS DTACK* WRITE D[31:24] WRITE D[15:8] D[15:8] WRITE D[23:16] WRITE D[7:0] D[7:0] MOTOROLA GATEWAY BOARD 7 For More Information On This Product, Go to: www.freescale.com F
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Freescale Semiconductor, Inc. Figure 3: Interrupt-Acknowledge Operation PS1 PS1 PS2 PS3 PS4 PS5 PS1 PS1 PS1 PS2 PS3 PS4 PS5 PS1 PS1 PS1 w w S0 S2S4S6 w w w S0 S2 S4 S6 w w w CLOCK TS* R/W* 11 TT[1:0] ATM SIZ[1:0] 01 01 VECTOR AD[31:24] AD[23:5] IPL IPL AD[4:2] LEVEL LEVEL AD[1:0] 01 or 01 or DA*[1:0] 10 10 AVEC* IPL*[2:0] FC[2:0] A[23:4] IPL LEVEL IPL LEVEL A[3:1] A0 AS* UDS LDS DTACK* D[15:8] VECTOR D[7:0] IACK CYCLE IACK CYCLE (VECTOR NUMBER (AUTOVECTORED) ACQUISITION) 8 GATEWAY BO
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Freescale Semiconductor, Inc. 7.0 PLD State Diagram Figure 4: SimpliÞed PLD State Diagram TS Reset TS Begin a TS 68EC000 cycle TS Wait for Grant to No beginning Grant ColdFire of ColdFire cycle Assert other control BR68K BR68K BR68K signals BR68K Data Grant to Acknowledge BDCF No 68EC000 to the DTACK Grant Wait Bus Master for MCF5202 Acknowledge BDCF from 68EC000 DTACK 8.0 PLD ABEL Code MODULE gateway TITLE 'The controlling signals between a 5202 and a 68EC000' gateway device 'i
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Freescale Semiconductor, Inc. "pLSI property 'LOCK ISPMODE 30'; pLSI property 'LOCK AD0 38'; pLSI property 'LOCK MODE 40'; pLSI property 'LOCK SIZ0 41'; pLSI property 'LOCK RnW 42'; pLSI property 'LOCK DTACK 43'; pLSI property 'LOCK TS 44'; pLSI property 'LOCK AENORM 3'; pLSI property 'LOCK AEIACK 4'; pLSI property 'LOCK FC2 12'; pLSI property 'LOCK FC1 13'; pLSI property 'LOCK FC0 14'; pLSI property 'LOCK BG68K 16'; pLSI property 'LOCK BGCF 20'; pLSI property 'LOCK LDAT 22'; pLSI prope
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Freescale Semiconductor, Inc. !BG68K pin 16 istype 'output'; "nBG68K !BGCF pin 20 istype 'output'; "nBGCF LDAT pin 22 istype 'output'; "(!nLE16_8) - 0=transparent latches, L-2-H=latches data !OEBA8 pin 23 istype 'output'; "nOEBA8 =0=HIZ, 1=output from B (TDAT) to A (AD) enabled !OEAB8 pin 24 istype 'output'; "nOEAB8 =0=HIZ, 1=output from A (AD) to B (TDAT) enabled !OEBA16 pin 25 istype 'output'; "nOEBA16=0=HIZ, 1=output from B (TDAT) to A (AD) enabled !OEAB16 pin 26 istype 'output
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Freescale Semiconductor, Inc. ATMA.clk = TS; "ATM is latched when TS is asserted NQ1.ar = RSTI; NQ2.ar = RSTI; NQ1.clk= PCLK; "Clock NegClk machine 1 with pos clk NQ2.clk= !PCLK; "Clock NegClk machine 2 with the inverted pos clk bsreg.clk = PCLK; bsreg.ar = RSTI; "Output enables AS.oe = !BG68K; Òenable when the 68K is not granted the bus UDS.oe = !BG68K; Òenable when the 68K is not granted the bus LDS.oe = !BG68K; "enable when the 68K is not granted the bus FC0.oe = !BG68K; "enable when
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Freescale Semiconductor, Inc. "Function Codes for EC000 - (See NOTE 1) " FC2 = ( (ATM & Normal-Access) # (IACK-Access) ) FC2 = ( ATM # (TT1&TT0) ); " FC1 = ( (ATMA & Normal-Access) # (IACK-Access) ) FC1 = ( ATMA # (TT1&TT0) ); " FC0 = ( (!ATMA & Normal-Access) # (IACK-Access) ) FC0 = ( !ATMA # (TT1&TT0) ); "----------------------------------------------------------------------------------------- STATE_DIAGRAM psreg; STATE PS0: "RESET and waiting for TS to de-assert IF TS THEN PS0; "Wait
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Freescale Semiconductor, Inc. STATE BS1: "Got a Request, wait for CF to quit driving the bus BGCF=0; BG68K=0; "Do not assert either Grant IF !BDCF THEN "If CF is not driving the bus, BS2; "then goto state 2 ELSE "else if CF is driving the bus, BS1; "stay in state 1 STATE BS2: "Done driving the bus, give the bus to 68K, wait for Request to go away BGCF=0; "Do not assert Grant to CF BG68K=1; "Assert Grant to 68K IF BR68K THEN "If 68K is still requesting the bus, BS2; "then stay in stat
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J3 10 26 27 9 1 J1 J2 61 43 60 44 Freescale Semiconductor, Inc. 9.0 Block Diagram Figure 5: Gateway Board Block Diagram 68EC000 ColdFire PLD Connector MCF5202 (68-pin PLCC) B D A M D A/D 10.0 Gateway Board Physical Layout Figure 6: Physical Layout (Actual Size) Component Side Solder Side 2 in. MOTOROLA GATEWAY BOARD 15 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... ISP J3 BDM U7 1 2 U2 26 10 U4 9 U8 J2 J1 1 U5 U6 61 U1 44 60 25
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Freescale Semiconductor, Inc. 11.0 Gateway Board Bill Of Material Table 5: Bill Of Material ITEM QTY MANUFACTURER PART NO. REF. DES. DESCRIPTION 1 1 Motorola XCF5202PU33A U1 IC, MCF5202, 33 MHz, 100pin, TQFP 2 1 Lattice ISPLSI1016-90LT44 U2 IC, PLD, 44 pins, TQFP 3 4 Motorola MC74F573DW U3-U5, U9 IC, 74F573, 20 pins, SOL20 4 3 Motorola MC74F543DW U6-U8 IC, 74F543, 24 pins, SOL24 5 4 Venkel CR1206-8W-103JT R1-R4 Res, 10K, 5%, 1/8W, 1206 6 4 Venkel CR1206-8W-472JT R5-R8 Res, 4.7K, 5%,
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Freescale Semiconductor, Inc. 12.0 ColdFire Gateway Board Schematics (1 of 2) U1 U9 MCF5202 74F573 0.01UF 1 OE AEUPPER ISPEN GND 87 11 CLK CLK 39 ADLT C R/W RNW 10 PF 35 67 RST TT0 nRST TT0 19 2 D0 A16 AD16 Q0 36 VCC GND TT1 TT1 3 18 D1 A17 AD17 Q1 41 SIZ0 SIZ0 33 UF 74 TCK 4 17 D2 A18 AD18 Q2 42 SIZ1 SIZ1 VCC 16 GND 73 TMS/BKPT 5 BKPT D3 A19 63 AD19 Q3 ATM ATM 72 TDI/DSI 6 15 DSI D4 Q4 A20 AD20 71 TDO/DSO 14 7 0.1 UF DSO D5 Q5 A21 AD21 40 13 70 TRST/DSCLK 8 DSCLK TS nTS D6 Q6 A22 AD22
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Freescale Semiconductor, Inc. ColdFire Gateway Board Schematics (2 of 2) J1 / B J1 / C J1 / D J1 / A EC000 CONN EC000 CONN EC000 CONN EC000 CONN A12 D12 RNW 10 nIPL0 27 44 61 A13 D11 nDTACK 11 FC2 28 45 62 nBG68K FC1 A14 46 D10 63 12 29 nBR68K FC0 A15 47 D9 64 13 30 VCC A0 A16 48 D8 65 14 31 VCC A1 A17 49 D7 66 15 32 CLK A2 A18 50 D6 67 16 33 A19 D5 GND 17 A3 34 51 68 GND GND A20 GND 18 35 52 1 MODE A4 VCC D4 19 36 53 2 A21 D3 nHALT A5 54 3 20 37 A22 D2 nRST A6 55 4 21 38 A23 D1 A7 56 5
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Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages. ÒTypic
