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AMD SB600
Register Reference Manual
(Public Version)
Technical Reference Manual
Rev. 3.03
P/N: 46155_sb600_rrg_pub_3.03
©2008 Advanced Micro Devices, Inc.
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Trademarks AMD, the AMD Arrow logo, Athlon, and combinations thereof, ATI, ATI logo, Radeon, and Crossfire are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Microsoft and Windows are registered trademarks and Windows Vista is trademark of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer
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Table of Contents 1 Introduction .............................................................................................................7 1.1 About this Manual........................................................................................................................... 7 1.2 Nomenclature and Conventions..................................................................................................... 7 1.2.1 Recent Updates ..........................................
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2.5 AC ’97 Controller Functional Descriptions ................................................................................. 198 2.5.1 Audio Registers (Device 20, Function 5)............................................................................................198 2.5.1.1 PCI Configuration Registers ............................................................................................................................... 198 2.5.1.2 Audio Memory Mapped Registers ..............
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List of Figures Figure 1 SB600 PCI Internal Devices ..........................................................................................................................11 Figure 2 SB600 PCI Internal Devices and Major Function Blocks ...............................................................................12 Figure 3 PCI Configuration Spaces for OHCI...............................................................................................................45 Figure 4 SMBus/
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List of Tables Table 1-1: Register Description Table Notation—Example............................................................................................7 Table 2-1 HcRevision Register ....................................................................................................................................68 Table 2-2 Legacy Support Registers............................................................................................................................68 Tab
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1 Introduction 1.1 About this Manual This manual is a register reference guide for the AMD SB600 Southbridge. It integrates the key I/O, communications, and audio features required in a state-of-the-art PC into a single device. It is specifically designed to operate with AMD’s RADEON IGP Xpress family of integrated graphics processor products in both desktop and mobile PCs. 1.2 Nomenclature and Conventions 1.2.1 Recent Updates Updates recent to each revision are highlighted in red.
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Register Information Value/Content in the Example Register name Latency Timer Read / Write capability R = Readable RW W = Writable RW = Readable and Writable Register size 8 bits Register address(es)* Offset: 0Dh Field name Latency Timer (R/W) Field position/size 7:0 Field default value 00h Field description “This bit … 8 clocks.” Field mirror information Brief register description Latency Timer. Reset Value: 00h * Note: There maybe more than one address; the conven
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1.3 Features of the SB600 CPU Interface Supports serial interrupt on quiet and Supports both Single and Dual core AMD continuous modes CPUs DMA Controller Desktop: Athlon 64, Athlon 64 FX, Athlon 64 X2, Sempron, Opteron, dual-core Two cascaded 8237 DMA controllers Opteron Supports PC/PCI DMA Mobile: Athlon XP-M, Mobile Athlon 64, Supports LPC DMA Turion 64, Mobile Sempron Supports type F DMA PCI Host Bus Controller LPC host bus controller Supports PCI Rev. 2.3 speci
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AC Link interface Supports for both audio and modem codecs RTC (Real Time Clock) Compliant with AC-97 codec Rev. 2.3 256-byte battery-backed CMOS RAM 6/8 channel support on audio codec Hardware supported century rollover Multiple functions for audio and modem RTC battery monitoring feature Codec operations Power Management Bus master logic ACPI specification 2.0 compliant power Supports up to 3 codecs simultaneously management schemes Supports SPDIF output Supports C
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1.4 Block Diagrams This section contains two block diagrams for the SB600. Figure 1 shows the SB600 internal PCI devices with their assigned bus, device, and function numbers. Figure 2 shows the SB600 internal PCI devices and the major function blocks. ALINK-EXPRESS II AC97 Audio AB Bus 0 DEV 20 Function 5 AC97 B-LINK A-LINK Device ID 4382h PORT 1 PORT 0 4 PORTS SATA Controller 1 AC97 Modem Bus 0 DEV 18 Function 0 Bus 0 DEV 20 Device ID 4380h Function 6 Device ID 438Eh USB:OHCI x5 B
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XBUS ALINK-EXPRESS II AB B-LINK A-LINK PORT 1 PORT 0 AC97 Audio 4 PORTS SATA AC97 Controller AC97 Modem B-LINK HD Audio USB:OHCI 10 PORTS USB:EHCI Debug port ALINK 1 CHANNEL IDE LPC bus SMBUS /ACPI LPC PCI Bridge 6 PCI SLOTS SPI bus ROM RTC X1/X2 BUS Controler SIRQ GPIO SERIRQ# PICD[0] RTC_IRQ#, PIDE_INTRQ, APIC BM SIDE_INTRQ, USB_IRQ#, 8250 TIMER SPEAKER AC97INTAB, PIC AC97INTBB INTERRUPT controller ACPI / HW SMI SMBUS PM Monitor INTR PWRGOOD IGNNE#, GEVENT[7:0],SLPBUTTON CPURST, FERRB
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2 Register Descriptions: PCI Devices 2.1 SATA Registers (Device 18, Function 0) Note: Some SATA functions are controlled by, and associated with, certain PCI configuration registers in the SMBus/ACPI device. For more information refer to section 2.3: SMBus Module and ACPI Block (Device 20, Function 0). The diagram below lists these SATA functions and the associated registers. SATA SATA Enables SATA power saving SATA Interrupt Map register SATA Smart Power Control PCI_Reg: 5Ch AC/AFh
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Register Name Offset Address Serial ATA Capability Register 0 70h Serial ATA Capability Register 1 74h IDP Index 78h IDP Data 7Ch PHY Port0 Control 88h PHY Port1 Control 8Ch PHY Port2 Control 90h PHY Port3 Control 94h BIST pattern Count C0h PCI Target Control TimeOut Counter C4h Vendor ID - R - 16 bits - [PCI_Reg:00h] Field Name Bits Default Description Vendor ID 15:0 1002h This register holds a unique 16-bit value assigned to a vendor. Combined with the device ID, it iden
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Status - RW - 16 bits - [PCI_Reg:06h] Field Name Bits Default Description Reserved 2:0 Reserved. Interrupt Status 3 0b Interrupt status bit. Complies with the PCI 2.3 specification. Capabilities List 4 1b Read Only. Hardwired to 1 to indicate that the Capabilities Pointer is located at 34h. 66MHz Support 5 1b 66MHz capable. This feature is supported in the SATA controller. Reserved 6 Reserved. Fast Back-to-Back 7 0b Read Only. Hard-wired to ‘0’ to indicate that it is fast bac
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Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h] Field Name Bits Default Description Note: This field is only writeable when PCI_Reg:40h[0] is set. Sub-Class Code Program Interface Controller Type 01 8F IDE 06 01 AHCI 04 00 RAID Cache Line Size - RW - 8 bits - [PCI_Reg:0Ch] Field Name Bits Defa
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Base Address 2 - RW - 32 bits - [PCI_Reg:18h] Field Name Bits Default Description Resource Type Indicator 0 1b This bit is wired to 1 to indicate that the base address field in this register maps to I/O space. Reserved 2:1 Reserved. Secondary IDE CS0 31:3 0000_ Base Address for Secondary IDE Bus CS0. This register is Base Address 0000h used for native mode only. Base Address 2 is not used in compatibility mode. Base Address 3 - RW - 32 bits - [PCI_Reg:1Ch] Field Name Bits Defau
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Min_gnt - R - 8 bits - [PCI_Reg:3Eh] Field Name Bits Default Description Minimum Grant 7:0 00h This register specifies the desired settings for how long of a burst the SATA controller needs. The value specifies a period of time in units of ¼ microseconds. Hard-wired to 0’s and always read as 0’s. Max_latency - R - 8 bits - [PCI_Reg:3Fh] Field Name Bits Default Description Maximum Latency 7:0 00h This register specifies the Maximum Latency time required before the SATA controller a
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MSI Control - RW- 32 bits - [PCI_Reg:50h] Field Name Bits Default Description Capability ID 7:0 05h Read-Only. Capability ID. It indicates that this is and MSI capability ID. Capability Next Pointer 15:8 70h Read-Only. Next Pointer (hard wired to 70h, points to Index Data pair capability Message Signaled 16 0b MSI Enable. Interrupt Enable Multiple Message 19:17 010b Multiple Message Capable. Capable Multiple Message Enable 22:20 000b Multiple Message Enable. MSI 64-bit Address
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PCI Power Management Control And Status - RW- 16 bits - [PCI_Reg:64h] Field Name Bits Default Description Power State 1:0 00b This field is used both to determine the current power state of the HBA and to set a new power state. The values are: 00 – D0 state 11 – D3 state HOT The D1 and D2 states are not supported. When in the D3 state, the configuration space is available, but the HOT register memory spaces are not. Additionally, interrupts are blocked. Reserved 7:2 Reserved
