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AN 9.6
SMSC LAN91C111 32/16/8-Bit Three-In-
One Fast Ethernet Controller -
Technical Reference Manual
1 Overview
This Technical Reference Manual provides detailed part-specific information and general system
design guidelines for the SMSC LAN91C111. Hardware engineers and software engineers should be
familiar with this material before interfacing the SMSC LAN91C111 to a microprocessor or
microcontroller.
This Manual is an active document and will be updated as required. The most recent versi
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller Collision Detection Encoder Decoder Scrambler De-scrambler Squelch Circuits Clock & Data Recovery AutoNegotiation & Link Twisted Pair Transmitter Twisted Pair Receiver EEPROM MII INTERFACE Control Control Control Control Control Control Arbiter 8-32 bit TPO Bus Ethernet 10/100 Interface Protocol Address Control MMU PHY Unit TX/RX DMA Handler FIFO Pointer (EPH) TX Data TXD[0-3] WR 32-bit Data FIFO 8K Byte TPI Dynamicall
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3 Description Of Bus Interface Unit (BIU) This section is intended to aid design engineers connecting the SMSC LAN91C111 device to a microprocessor or microcontroller. This section will discuss in detail the functional block, and the individual control signals of the LAN91C111 involved in the connection between the device and an associated microprocessor / microcontroller. 3.1 Pin Function Listing The LAN91C111 consist of the fo
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller Figure 3.1 BIU Section of functional Block Diagram For those interested in designing connected to an ISA bus, SMSC provides both a reference design and evaluation board. Please contact your SMSC Sales Representative or Distributor for information regarding either of these products. The Data Sheet also contains block diagrams of a typical ISA, EISA, and VL-Bus based designs. 3.2 ISA Bus The LAN91C111 supports both an asynchronous
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.3.1 Address Decoding Example BYTE A3 A2 A1 IO-ADDRESS ENABLE NOTES 0 0 0 300 nBE0 Assert nBE0 to enable the lowest byte 0 0 0 301 nBE1 Assert nBE1 to enable the second lowest byte 0 0 1 302 nBE0 Assert nBE0 to enable the lowest byte 0 0 1 303 nBE1 Assert nBE1 to enable the second lowest byte 0 1 0 304 nBE0 Assert nBE0 to enable the lowest byte 0 1 0 305 nBE1 Assert nBE1 to enable the second lowest byte 0 1 1 306 nBE0 Assert n
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.4.1 Typical Signal Connection with Asynchronous Buses LAN91C111 HOST SIGNALS SIGNALS NOTES A1-A15 A1-A15 Address D0-D31 D0-D31 Data nBE [0-3] nBE[0-3] Byte Enable AEN/CS AEN Active low address enable. It can be connected to ship select if the chip select timing matches to AEN Reset Reset Reset nADS/Ground nADS Active low address latch signal. It can be tied low, please see the timing diagrams figure 24 to 26 of the database
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.4.2 Signal Connection with Asynchronous Interfacing Figure 3.2 Asynchronous Interface Connection 3.5 Synchronous Interface (VL-Bus) The LAN91C111 also supports a 32-bit synchronous interface. This interface is intended to duplicate the VESA standard (www.vesa.org), otherwise known as the VL-Bus. Since this interface is not as widely understood as the ISA bus we will go over this interface in some detail in this document. The
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.5.1 Typical Connection with Synchronous Interface (VL-Bus) HOST (VL BUS) LAN91C111 SIGNAL SIGNAL NOTES A2-A15 A2-A15 Address bus used for I/O space and register decoding, latched by nADS rising edgeand transparent on nADS low time. M/nIO AEN Qualifies valid I/O decoding - enabled access when low. This signal is latched by nADS rising edge and transparent on nADS low time. W/nR W/nR Direction of access. Sampled by the LAN9
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.5.2 Signal Connection with Synchronous Interfacing +VCC nR W/nR W/nR D A2-A15 nWR A2-A15 A1 LCLK LCLK nVLBUS AEN M/nIO (Open) nDATACS nRESET RESET LAN91C111 IRQn INTR0 D0-D31 D0-D31 nRDYRTN nRDYRTN nBE0-nBE3 nBE0-nBE3 nADS nADS nCYCLE delay1 O.C. nSRDY nLRDY simulated nLDEV O.C. nLDEV Figure 3.3 Synchronous Interface (VL-Bus) Connection 3.5.3 Address Bus The 13 address lines form the address bus. It is presented to the LAN
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.5.6 NRDYRTN Ready Return is an input signal generated by the host controller to establish a handshake signal to inform the LAN91C111 that the cycle has ended. For LCLK speeds up to 33Mhz, nRDYRTN is typically asserted in the same LCLK cycle as nSRDY is asserted. For higher LCLK speed, nRDYRTN may trail nSRDY by one LCLK cycle due to signal resynchronization. In Non-VL-Bus mode, Ready Return is an input signal generated by the
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.5.11 32-Bit Access and nBE0-nBE3 The LAN91C111 can operate in 32, 16, or 8-bit mode. Since the registers are assigned to different banks, changing bank is required if accessing to registers at other bank. Changing bank can be done by writing to Offset E – Bank Select Register, however offset C, D, E, F are in the same double word (32-bit) alignment, writing a double word to offset C, will only write to offset E, and will not
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller t23 t20 t10 t24 Clock t9 Address, AEN, nBE[3:0] Valid t8 nADS t16 W/nR t11 nCYCLE Read Data Valid t21 t21 nSRDY nRDYRTN Figure 3.4 Synchronous Write Cycle - nVLBUS=0 PARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t17
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller accomplished through external circuitry. Signal W/nR has to be asserted high no later than nCYCLE assertion. 3.6.2 Write Cycle Data Phase - Cycle End During next rising edge after de-assertion of nCYCLE, write data has to be presented to the LAN91C111. The data bus will need to be stable at least 15nS prior to the rising edge of LCLK and are required to hold 4nS, as specified by timing parameter t18 and t20. nSRDY (translated
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller PARAMETER MIN TYP MAXUNITS t11 nCYCLE Hold after LCLK Rising 3ns (Non-Burst Mode) t16 W/nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising 4ns (Read) t21 nSRDY Delay from LCLK Rising 7 ns t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold after LCLK Rising 3 ns 3.6.4 Read Cycle Address Phase – Cycle Start As with the Write Cycle, the Address Bus, AEN, and the Byte Enable lines (nBE0-nBE3) are required to be stable
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller 3.7.1 The Use of NDATACS Direct access to the Data Register is controlled via the nDATACS pin. This is can be accomplished whether the LAN91C111 is configured for synchronous or asynchronous operations. Accessing the LAN91C111 via the nDATACS pin bypasses the internal Bus Interface Unit (BIU) decoders and . All accesses are accesses designated by the nDATACS are steered towards the Data Register only 32-bits in nature and used t
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller READ When set (1) the operation is a read; when cleared (0) the operation is a write. NOT EMPTY This read-only bit indicates whether the Write Data FIFO is empty or not. The FIFO is not empty when this bit is set. POINTER HIGH These bits comprise the upper three bits of the address. POINTER LOW These bits comprise the lower 8-bits of the address. Remember that all access is 32-bits in nature and therefore the lower two bits are i
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller t2 nDATACS t3A t4 Read Data Valid t6A t6A t1 t5 nRD, nWR t5A Write Data D0-D31 Valid Figure 3.8 Asynchronous Cycle - nADS=0 (nDATACS Used to Select Data Register; Must Be 32 Bit Access) PARAMETER MIN TYP MAX UNITS t1 nDATACS Setup to nRD, nWR 2ns Active t2 nDATACS Hold After nRD, nWR 5ns Inactive (Assuming nADS Tied Low) t3A nRD Low to Valid Data 30 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inactive 10 ns t5A
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller nRDYRTN can be used to insert wait states. In Synchronous mode back to back time between read or write is limited by access times. From timing diagram, it is 3 clocks for read and 2 clocks for write, but it has to be bigger than 100ns for read and 80ns for write. 3.10 Burst Mode Write Operation The timing diagram below details a burst mode write operation and shows three separate packets of data being transferred. The first two
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller This timing diagram examples and details a burst mode write operation. The nDATACS pin remains asserted throughout the cycle and the nCYCLE pin is used to control the burst data. As long as nCYCLE remains asserted, data can be written on each rising edge of LCLK. In the above timing diagram nRDYRTN is used to insert a wait state between the second and third data packet. The assertion of nRDYRTN is required at a minimum of 10nS b
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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller PARAMETER MIN TYP MAX UNITS t15 nRDYRTN Hold after LCLK Falling 10 ns t17 W/nR Setup to LCLK Falling 15 ns t17A W/nr Hold After LCLK Falling 3 ns t19 Data Delay from LCLK Rising (Read) 5 15 ns As you can see by the timing diagram and subsequent timing parameter table the nDATACS signal is used to indicate that the cycle is a burst mode direct operation. As long as nDATACS remains asserted the LAN91C111 will continue to read data
