Summary of the content on the page No. 1
DS33R11
Ethernet Mapper with Integrated
T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
The DS33R11 extends a 10/100 Ethernet LAN
RMII) Half/Full Duplex with Automatic Flow
segment by encapsulating MAC frames in HDLC or
Control
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
Integrated T1/E1/J1 Framer and LIU
The device performs store-and-forward of packets
HDLC/LAPS Encapsulation with
with fu
Summary of the content on the page No. 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver TABLE OF CONTENTS 1 DESCRIPTION ................................................................................................................................... 9 2 FEATURE HIGHLIGHTS.................................................................................................................. 11 2.1 GENERAL......................................................................................................................
Summary of the content on the page No. 3
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.14.1 DTE and DCE Mode .............................................................................................................................58 9.15 ETHERNET MAC ........................................................................................................................... 59 9.15.1 MII Mode Options..................................................................................................................
Summary of the content on the page No. 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.17.4 FIFO Information...................................................................................................................................96 10.17.5 Receive Packet-Bytes Available ...........................................................................................................96 10.18 LEGACY FDL SUPPORT (T1 MODE) ............................................................................................
Summary of the content on the page No. 5
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 12.4 E1 MODE.................................................................................................................................... 308 13 OPERATING PARAMETERS ........................................................................................................ 313 13.1 THERMAL CHARACTERISTICS....................................................................................................... 314 13.2 MII INTERF
Summary of the content on the page No. 6
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram ................................................................................................................................20 Figure 6-2. Block Diagram of T1/E1/J1 Transceiver ................................................................
Summary of the content on the page No. 7
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................ 307 Figure 12-20. Receive-Side Timing ......................................................................................................................... 308 Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) .......................................................... 308 Figure 1
Summary of the content on the page No. 8
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 25 Table 9-1. Clocking Options for the Ethernet Interface .......................................................
Summary of the content on the page No. 9
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 1 DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports, Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver. The packet interface consists o
Summary of the content on the page No. 10
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethernet mapper. There are a few things to note when porting a DS33Z11 application to this device: • The SPI and hardware modes are not supported. • RSER has been renamed to RSERI. • RCLK has been renamed to RCLKI. • TSER has been renamed to TSERO. • TCLK has been renamed to TCLKE. The integrated T1/E1/J1 transceiver is software compatible with the DS215
Summary of the content on the page No. 11
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2 FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and reference designs • Reference design routes on a two-layer PC board • Programmable output clocks for fractional T1, E1, H0, and H12 applications 2.2 Microprocessor Interface • Parall
Summary of the content on the page No. 12
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast load and unload features for FIFOs • SS7 support for FISU transmit and receive • Independent 128-byte Rx and Tx buffers with interrupt support • Access FDL, Sa, or single/multiple DS0 channels • DS0 access includes Nx64 or Nx56 • Compatible with polled or interrupt driven environments • Bit-oriented cod
Summary of the content on the page No. 13
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.9 T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation • Fully software configurable • Short-haul and long-haul applications • Automatic receive sensitivity adjustments • Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1 applications • Receive level indication in 2.5dB steps from -42.5dB to -2
Summary of the content on the page No. 14
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.12 T1/E1/J1 Framer • Fully independent transmit and receive functionality • Full receive and transmit path transparency • T1 framing formats include D4 (SLC-96) and ESF • Detailed alarm and status reporting with optional interrupt support • Large path and line error counters for: o T1: BPV, CV, CRC6, and framing bit errors o E1: BPV, CV, CRC4, E-bit, and frame alignment errors • Timed or manual update modes • DS1 idle c
Summary of the content on the page No. 15
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom patterns including QRSS • User-defined repetitive patterns • Daly pattern • Error insertion single and continuous • Total bit and errored bit counts • Payload error insertion • Error insertion in the payload portion of the T1 frame in the transmit path • Errors can be inserted over the entire frame or selected
Summary of the content on the page No. 16
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.15 Specifications Compliance The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications. RFC1662—PPP in HDLC-like Framing RFC2615—PPP over SONET/SDH X.86—Ethernet over LAPS RMII—Industry Im
Summary of the content on the page No. 17
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge, available on our website at www.maxim-ic.com/telecom. Figure 3-1. Ethernet-to-WAN Extension (With or Without Fram
Summary of the content on the page No. 18
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media Independent Interface • RMII: Reduced Media Independent Interface • WAN: Wide Area Network Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interf
Summary of the content on the page No. 19
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation. The integrated transceiver can be software configured for T1, E1, or J1 operation. It is composed of a line interface unit (LIU), framer, two additional HDLC controllers
Summary of the content on the page No. 20
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram μP Port CLAD CLAD SYSCLKI (RMII MODE) RXD[0:1] RX_CLK TTIP MUX CRS_DV RX_ERR TRING HDLC REF_CLK BERT ARBITER REF_CLKO HDLC TX_EN RTIP MUX TXD[0:1] RRING MDC MDIO JTAG2 JTAG1 SDRAM PORT NOTE: SOME PINS NOT SHOWN. THE BLOCK IN THE DIAGRAM LABELED “T1/E1/J1 TRANSCEIVER” IS DIVIDED INTO THREE FUNCTIONAL BLOCKS: LIU, FRAMER, AND
