Summary of the content on the page No. 12
Section Page Description 10.2.13 MCS0 Control 258 Description added Register (MCSCR0) Bit 6—CS2/CS0 Select (CS2/0) Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7. 10.3.4 Synchronous 290 Bank Active description added DRAM Interface … .In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. The bank active mode should not be used unless the bus width for all areas
Summary of the content on the page No. 13
Section Page Description 16.4 SCIF Interrupts 550 Description amended When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. When data exceeding the transmit trigger number is written to the transmit data register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it. When the RDF flag in SCSSR is set to 1, an RX
Summary of the content on the page No. 14
Section Page Description 20.3 Bus Master 622 Figure amended Interface Upper byte read Figure 20.2 A/D Data Register Access CPU Module internal data bus Bus Operation (Reading receives interface H'AA40) data H'AA TEMP [H'40] ADDRn H ADDRn L n = A to D [H'AA] [H'40] Lower byte read CPU Bus Module internal data bus receives interface data H'40 TEMP [H'40] ADDRn H ADDRn L n = A to D [H'AA] [H'40] 23.1 Absolute 657 Caution added Maximum Ratings 2.Until voltage is applied to all power supplies,
Summary of the content on the page No. 15
Section Page Description 23.3.6 Synchronous 690 Tnop cycle deleted from figure DRAM Timing Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Figure 23.31 Synchronous DRAM CKIO Burst Read Bus Cycle t t AD AD (RAS Down, Same Row Address, CAS Latency A25 to A16 Row address = 2) t t AD AD Read command A12 or A10 t t AD AD Column address A15 to A0 t t CSD3 CSD3 CSn t RWD t RWD RD/WR t RASD2 RAS t CASD2 t CASD2 CAS t DQMD t DQMD DQMxx t t t t RDS2 RDH2 RDS2 RDH2 D31 to D0 t t BSD BSD BS CKE (High) t t DAKD1 DAKD1 DAC
Summary of the content on the page No. 16
Section Page Description A.2 Pin Specifications 723 Function information amended for V –RTC, V –PLL1, V – CC CC CC PLL2, and V CC Table A.2 Pin Specifications Pin Pin No. Pin No. I/O Function (FP-208C, (BP- FP-208E) 240A) V – 3 E2 Power RTC oscillator power CC RTC supply supply (2.0/1.9/1.8/1.7 V) V – 145 F16, Power PLL power supply CC PLL1 150 E17 supply (2.0/1.9/1.8/1.7 V) V – CC PLL2 V 29, 81, L3, L4, Power Internal power supply CC 134, 154, U11, T11, supply (2.0/1.9/1.8/1.7 V) 175 J17, J
Summary of the content on the page No. 17
Contents Section 1 Overview and Pin Functions.......................................................................... 1 1.1 SH7709S Features .............................................................................................................1 1.2 Block Diagram .................................................................................................................. 6 1.3 Pin Description .........................................................................................
Summary of the content on the page No. 18
3.4 MMU Functions ................................................................................................................69 3.4.1 MMU Hardware Management ............................................................................. 69 3.4.2 MMU Software Management............................................................................... 69 3.4.3 MMU Instruction (LDTLB) ................................................................................. 70 3.4.4 Avoiding Synonym Proble
Summary of the content on the page No. 19
5.1.2 Cache Structure .................................................................................................... 103 5.1.3 Register Configuration ......................................................................................... 105 5.2 Register Description .......................................................................................................... 105 5.2.1 Cache Control Register (CCR)............................................................................. 10
Summary of the content on the page No. 20
Section 7 User Break Controller...................................................................................... 149 7.1 Overview ........................................................................................................................... 149 7.1.1 Features ................................................................................................................ 149 7.1.2 Block Diagram ...................................................................................
Summary of the content on the page No. 1
SH7709S Group
Hardware Manual
32
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7700 Series
Rev.5.00
2003.9.18
Summary of the content on the page No. 2
Summary of the content on the page No. 3
Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7709S Group Hardware Manual REJ09B0081-0500O
Summary of the content on the page No. 4
Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflam
Summary of the content on the page No. 5
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unuse
Summary of the content on the page No. 6
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) O
Summary of the content on the page No. 7
Preface This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions necessary for configuring a user system. This LSI is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timer, three serial communication interfaces, real- time clock (RTC), use break controller (UBC), bus state controller (BSC) and I/O ports. This LSI can be used as a microcomputer for devices that require both high speed and l
Summary of the content on the page No. 8
• User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Embedded Workshop User’s Manual ADE-702-201 Rev. 5.00, 09/03, page viii of xliv
Summary of the content on the page No. 9
List of Items Revised or Added for This Version Section Page Description 1.2 Block Diagram 6 ASERAM deleted from figure Figure 1.1 Block BRIDGE Diagram UDI INTC CPG/WDT External bus interface ASERAM deleted from legend 2.5.1 Processor States 53 Description amended In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of on-chip supporting modules other
Summary of the content on the page No. 10
Section Page Description 5.4.3 Examples of 115, (1) Invalidating a Specific Entry Usage 116 Description amended A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to. In the followin
Summary of the content on the page No. 11
Section Page Description 8.3.3 Precautions 187 Newley added when Using the Sleep Mode 8.5.1 Transition to 191 Note *3 added to bit table Module Standby Note: 3. Before putting the RTC into module standby status, first Function access one or more of the RTC, SCI, and TMU registers. The RTC may then be put into module standby status. 9.3 Clock Operating 210 2. under cautions amended Modes The peripheral clock frequency should not be set higher than the Table 9.4 Available frequency of the
