Summary of the content on the page No. 1
DSP56012UM/D
Rev. 0
Published 11/98
DSP56012
24-Bit Digital Signal Processor
User’s Manual
Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598
Summary of the content on the page No. 2
DSP56012UM/D Rev. 0 Published 11/98 This document (and other documents) can be viewed on the World Wide Web at http://www.motorola-dsp.com. This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual, User’s Manual, and Technical Data. OnCE is a trademark of Motorola, Inc. ª MOTOROLA INC., 1998 Order this document by DSP56012UM/AD Motorola reserves the right to make changes without further notice to any products
Summary of the content on the page No. 3
Table of Contents 1.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1 Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.2 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2 DSP56012 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3 DSP56012 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . 1-8 1.3.1 Peripheral Modules. . . . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 4
2.6 HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.7 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-13 2.8 SERIAL AUDIO INTERFACE (SAI) . . . . . . . . . . . . . . . . . . 2-16 2.8.1 SAI Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.8.2 SAI Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) . . . . . . . . 2-18 2.10 DIGITAL AUDIO INTERFACE (DA
Summary of the content on the page No. 5
4.4.4.1.2 HCR HI Transmit Interrupt Enable (HTIE)—Bit 1 . 4-15 4.4.4.1.3 HCR HI Command Interrupt Enable (HCIE)—Bit 2 4-15 4.4.4.1.4 HCR HI Flag 2 (HF2)—Bit 3 . . . . . . . . . . . . . . . . . 4-15 4.4.4.1.5 HCR HI Flag 3 (HF3)—Bit 4 . . . . . . . . . . . . . . . . . 4-15 4.4.4.1.6 HCR Reserved—Bits 5, 6, and 7. . . . . . . . . . . . . . 4-16 4.4.4.2 HI Status Register (HSR). . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.4.2.1 HSR HI Receive Data Full (HRDF)—Bit 0. . . . . . . 4-16 4.4.4
Summary of the content on the page No. 6
4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only) . . . . . . . . . 4-31 4.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only) . . . . . . . . . 4-31 4.4.5.6.6 ISR Reserved—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.4.5.6.7 ISR DMA Status (DMA)—Bit 6 . . . . . . . . . . . . . . . 4-32 4.4.5.6.8 ISR Host Request (HOREQ)—Bit 7 . . . . . . . . . . . 4-32 4.4.5.7 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . 4-32 4.4.5.8 Receive Byte Registers (RXH, RXM, RXL) . . . . .
Summary of the content on the page No. 7
4.4.8.4.4 Overwriting the Host Vector . . . . . . . . . . . . . . . . . 4-66 4.4.8.4.5 Cancelling a Pending Host Command interrupt . . 4-66 4.4.8.4.6 Coordinating Data Transfers . . . . . . . . . . . . . . . . . 4-67 4.4.8.4.7 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 5.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE . 5-4 5.3 SHI CLOCK GENERATOR . . . . . . . . . . . . .
Summary of the content on the page No. 8
5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . 5-18 5.4.6.17 Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . . . . 5-18 5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22. . . . . . . . . . . . . . 5-19 5.5 CHARACTERISTICS OF THE SPI BUS. . . . . . . . . . . . . . . 5-19 2 5.6 CHARACTERISTICS OF THE I C BUS . . . . . . . . . . . . . . . 5-20 5.6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 2 5.6.2 I C Data Transfer Format
Summary of the content on the page No. 9
6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 106-14 6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11. . . . . 6-15 6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12. . . . 6-15 6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14 . . . . . . 6-16 6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15 . . . . . 6-16 6.3.3 SAI Receive Data Registers (RX0 and RX1) . . . . . . . . . 6-17 6.3.4 Transmitter Control/Status Register (TCS). . . . . . . . . . . 6-17 6.3.4.1 TCS Transmitter
Summary of the content on the page No. 10
8.3 DAX FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . 8-5 8.4 DAX PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5 DAX INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . 8-6 8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB) . . 8-7 8.5.2 DAX Audio Data Buffer (XADBUF). . . . . . . . . . . . . . . . . . 8-7 8.5.3 DAX Audio Data Shift Register (XADSR). . . . . . . . . . . . . 8-8 8.5.4 DAX Control Register (XCTR) . . . . . . . . . . . . . . . .
Summary of the content on the page No. 11
B.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2 PERIPHERAL ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.3 INTERRUPT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.4 INTERRUPT PRIORITIES . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.5 INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . B-3 B.6 PROGRAMMING SHEETS. . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Motorola xi
Summary of the content on the page No. 12
xii Motorola
Summary of the content on the page No. 13
List of Figures Figure 1-1 DSP56012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Figure 2-1 DSP56012 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 3-1 Memory Maps for PEA = 0, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-5 Figure 3-2 Memory Maps for PEA = 1, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6 Figure 3-3 Memory Maps for PEA = 0, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7 Figure 3
Summary of the content on the page No. 14
Figure 4-13 Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29 Figure 4-14 Host Processor Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . .4-37 Figure 4-15 Interrupt Vector Register Read Timing . . . . . . . . . . . . . . . . . . . .4-40 Figure 4-16 HI Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-40 Figure 4-17 DMA Transfer Logic and Timing . . . . . . . . . . . . . . . . . . . . . . . . .4-41 Figure
Summary of the content on the page No. 15
Figure 4-36 DMA Transfer and HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .4-61 Figure 4-37 Host to DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .4-63 Figure 5-1 Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . .5-4 Figure 5-2 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Figure 5-3 SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . .5-5 Figur
Summary of the content on the page No. 16
Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming . . . . . . .6-19 Figure 6-12 Transmitter Clock Polarity (TCKP) Programming . . . . . . . . . . . .6-20 Figure 6-13 Transmitter Relative Timing (TREL) Programming. . . . . . . . . . .6-20 Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming . . . . .6-21 Figure 7-1 GPIO Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 Figure 7-2 GPIO Circuit Diagram . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 17
List of Tables Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . 1-6 Table 1-2 DSP56012 Internal Memory Configurations . . . . . . . . . . . . . . . . 1-7 Table 1-3 Interrupt Starting Addresses and Sources . . . . . . . . . . . . . . . 1-13 Table 1-4 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . 1-15 Table 1-5 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . 1-17 Table 2-1 DSP56012 Functional Sig
Summary of the content on the page No. 18
Table 3-5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 Table 4-1 HI Registers after Reset—DSP CPU Side . . . . . . . . . . . . . . . .4-19 Table 4-2 HOREQ Pin Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25 Table 4-3 HI Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-26 Table 4-4 HOREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28 Tabl
Summary of the content on the page No. 19
Table B-2 Interrupt Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . B-6 Table B-3 Instruction Set Summary (Sheet 1 of 7). . . . . . . . . . . . . . . . . . . B-8 Motorola xix
Summary of the content on the page No. 20
xx Motorola
