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FUJITSU SEMICONDUCTOR
CM71-00101-5E
CONTROLLER MANUAL
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
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FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL FUJITSU LIMITED
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PREFACE ■ Objectives and intended reader The FR* family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit RISC based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required. This manual is written for engineers involved in the development of products using the FR family of microcontrollers. It is designed specifically for programmers working in as
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■ Organization of this manual This manual consists of the following 7 chapters and 1 appendix: CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU. CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU. CHAPTER 4 RESET AND "EIT" PROCESSING This chapter describes reset and "EIT" processing
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• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipm
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CONTENTS CHAPTER 1 FR FAMILY OVERVIEW .............................................................................. 1 1.1 Features of the FR Family CPU Core ................................................................................................. 2 1.2 Sample Configuration of an FR Family Device ................................................................................... 3 1.3 Sample Configuration of the FR Family CPU ..............................................................
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ............. 53 5.1 Pipeline Operation ............................................................................................................................ 54 5.2 Pipeline Operation and Interrupt Processing .................................................................................... 55 5.3 Register Hazards ..................................................................................................................
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7.35 MULU (Multiply Unsigned Word Data) ............................................................................................ 122 7.36 MULH (Multiply Half-word Data) ..................................................................................................... 124 7.37 MULUH (Multiply Unsigned Half-word Data) .................................................................................. 126 7.38 DIV0S (Initial Setting Up for Signed Division) ....................................
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7.82 MOV (Move Word Data in Source Register to Destination Register) ............................................. 178 7.83 MOV (Move Word Data in Source Register to Destination Register) ............................................. 179 7.84 MOV (Move Word Data in Program Status Register to Destination Register) ................................ 180 7.85 MOV (Move Word Data in Source Register to Destination Register) ............................................. 181 7.86 MOV (Move Word Data i
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7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 240 7.124 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 241 7.125 EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... 242 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) ............................................................
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Main changes in this edition Page Changes (For details, refer to main body.) Be sure to refer to the "Check Sheet" for the latest cautions on development. is changed. - ("Check Sheet" is seen at the following support page... is deleted.) "■ Objectives and intended reader" is changed. ( "FR" → "FR*" ) "■ Objectives and intended reader" is changed. ( " *: " is added. ) i "PREFACE" is changed. ( "■ Trademark" is added. ) "PREFACE" is changed. ( "The company names and brand names herein are the tr
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Page Changes (For details, refer to main body.) "4.3.1 User Interrupts" is changed. ( "External" → "User" ), ( "external" → "user" ) "■ Overview of User Interrupts" is changed. ( "External" → "User" ) "■ Overview of User Interrupts" is changed. ( "Interrupts are referred to as "external" when they originate outside the CPU." is deleted. ) 38 "■ Conditions for Acceptance of User Interrupt Requests" is changed. ( "External" → "User" ) "■ Conditions for Acceptance of User Interrupt Reque
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Page Changes (For details, refer to main body.) "7.15 AND (And Word Data of Source Register to Data in Memory)" is changed. 87 ( "Instruction bit pattern : 1000 0100 0010 0011" is added.) "7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed. 89 ( "Instruction bit pattern : 1000 0101 0010 0011" is added. ) "7.17 ANDB (And Byte Data of Source Register to Data in Memory)" is changed. 91 ( "Instruction bit pattern : 1000 0110 0010 0011" is added. ) "7.18 OR (Or Word Data
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Page Changes (For details, refer to main body.) "7.42 DIV3 (Correction when Remainder is 0)" is changed. 136 ( "Instruction bit pattern : 1001 1111 0110 0000" is added. ) "7.43 DIV4S (Correction Answer for Signed Division)" is changed. 137 ( "Instruction bit pattern : 1001 1111 0111 0000" is added. ) "7.44 LSL (Logical Shift to the Left Direction)" is changed. 138 ( "Instruction bit pattern : 1011 0110 0010 0011" is added. ) "7.47 LSR (Logical Shift to the Right Direction)" is changed. 141 (
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Page Changes (For details, refer to main body.) "7.67 LDUB (Load Byte Data in Memory to Register)" is changed. 163 ( "Instruction bit pattern : 0000 0010 0010 0011" is added. ) "7.69 ST (Store Word Data in Register to Memory)" is changed. 165 ( "Instruction bit pattern : 0001 0100 0010 0011" is added. ) "7.70 ST (Store Word Data in Register to Memory)" is changed. 166 ( "Instruction bit pattern : 0001 0000 0010 0011" is added. ) "7.72 ST (Store Word Data in Register to Memory)" is changed. 168 (
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Page Changes (For details, refer to main body.) "7.88 CALL (Call Subroutine)" is changed. ( "extension for use as the branch destination address" → "extension" ) "7.88 CALL (Call Subroutine)" is changed. ( "CALL 120H" → 185 " CALL label ... label: ; CALL instruction address + 122 " ) H "7.88 CALL (Call Subroutine)" is changed. ( "Instruction bit pattern : 1101 0000 1001 0000" is added. ) "7.89 CALL (Call Subroutine)" is changed. 186 ( "Instruction bit pattern : 1001 0111 000
