Summary of the content on the page No. 1
Application Report
SCPA033 - October 2002
PCI1520 Implementation Guide
Computer Connectivity Solutions
ABSTRACT
This document is provided to assist platform designers using the PCI1520 dual-socket PC
Card controller. Detailed information can be found in the PCI1520 data manual.
However, this document provides design suggestions for the various options when
designing in the PCI1520.
Contents
1 PCI1520 Typical System Implementation ..................................................................
Summary of the content on the page No. 2
SCPA033 Figures Figure 1. Typical System Implementation.......................................................................................................................3 Figure 2. Power Switch Implementation..........................................................................................................................5 Figure 3. EEPROM Implementation................................................................................................................................10 F
Summary of the content on the page No. 3
SCPA033 1 PCI1520 Typical System Implementation The figure below represents a typical implementation of the PCI1520 PC Card Controller. The device serves as a bridge between a PCI Bus and a PC Card interface. The PCI1520 will operate only with the PCI Bus as a primary bus and the PC Card interface as the secondary bus. The PC Card interface operates with both CardBus (32-bit) and 16-bit PC Cards. Vcc/Vpp TPS2226A Power Switch 4 3 P2C Bus Socket A PCI1520 CardBus Controller Socket B PME# 2 I2C Bu
Summary of the content on the page No. 4
SCPA033 2 Power Considerations 2.1 Internal Voltage Regulator One of the major differences between the PCI1520 and previous Texas Instruments CardBus controllers is that the PCI1520 uses an internal voltage regulator to power the core logic at 2.5V. This allows for a more than 50% reduction in power consumption over previous controllers. The voltage regulator is enabled using the VR_EN# pin. If VR_EN# is high, the voltage regulator is disabled and VRPORT serves as a 2.5V external input to power
Summary of the content on the page No. 5
SCPA033 3 Power Switch Implementation The following figure shows the serial interface between the PCI1520 and the TPS2226A power switch: VPPA CLOCK Socket A VCCA DATA PCI1520 TPS2226A VPPB VCCB LATCH Socket B Pull-down for Pulldown if I2C interface using internal (optional) clock Figure 2. Power Switch Implementation A power switch is necessary in order to control power to the PC Card sockets. When the 2 PCI1520 receives a socket power request, it sends the appropriate data across the P C interf
Summary of the content on the page No. 6
SCPA033 4 PCI Bus Interface The PCI1520 has a 33MHz, 32 bit PCI Interface compliant with PCI Local Bus Specification Revision 2.2. • PCLK, AD31:0, C/BE#3:0, PAR, DEVSEL#, FRAME#, STOP#, TRDY#, IRDY#, GNT#, and REQ# are required PCI signals. All except PCLK, GNT#, and REQ# are bussed signals. PCLK is a 33MHz point-to-point clock. GNT# and REQ# are point-to-point signals form the PCI bus arbitrator. • PERR#, SERR#, and LOCK# are optional PCI signals. PERR# and SERR# are bussed signals and should b
Summary of the content on the page No. 7
SCPA033 5 PC Card Interface There are two different modes on the PC Card interface. The first is 16-bit mode which is analogous to the legacy ISA bus. The second is 32-bit CardBus mode which is very similar to a PCI Bus. The terminal functions for these two modes are multiplexed and routed to the PC Card sockets. The following suggestions apply to the PC Card interface: • Pullup resistors for the PC Card interface have been integrated into the PCI1520. These include: A14/CPERR#, A15/CIRDY#, A19/
Summary of the content on the page No. 8
SCPA033 6 Miscellaneous Pin Interface 6.1 Multifunction Terminals The multifunction terminals (MFUNC6:0) can be programmed to serve many different roles using the Multifunction Routing register at PCI configuration offset 8Ch. The discrete ISA interrupts (IRQ15:2), INTA#, INTB#, and IRQSER are explained in Section 7 – Interrupt Configurations. CLKRUN#, D3STAT#, and RI_OUT# are discussed in Section 9 – Power Management Considerations. ZVSTAT, ZVSEL1#, and ZVSEL0# are used for ZV control. For more
Summary of the content on the page No. 9
SCPA033 7 Interrupt Configurations The PCI1520 provides system designers with great flexibility in configuring interrupts. The PCI1520 allows four interrupt modes which are selected via bits 2:1 of the Device Control register at PCI offset 92h. PCI interrupts are available on INTA# and INTB#. These signals are available on MFUNC0 and MFUNC1 respectively. The Multifunction Routing register at PCI configuration offset 8Ch must be programmed correspondingly. If MFUNC1 is not available (i.e. EEPROM
Summary of the content on the page No. 10
SCPA033 8 Software Considerations The PCI1520 is natively supported by Windows XP. The PCI1520 will be recognized natively as a Generic CardBus Controller under Windows 2000, Windows ME, and Windows 98SE. The device will function properly using this driver. However, it is recommended that new drivers provided by Texas Instruments be used for non-XP systems. These drivers have a few small tweaks and allow the device to be reported in Device Manager properly. Other operating systems are not suppor
Summary of the content on the page No. 11
SCPA033 The EEPROM loading map can be found in the data manual. The following is an example data file which could be loaded into the EEPROM for use with the PCI1520: ; EEPROM Programming Data for the PCI1520 Customer Board ; Configured for IRQ serialized interrupts and parallel PCI interrupts ; Register Data Description 00 0x01 ;Reference 1 01 0x03 ;04h Command Register, bit 8 (mapped from EEPROM bit 7), 6-5, 2-0 02 0x78 ;40h Sub-System Vendor ID Byte 0 03 0x56 ;40h Sub-System Vendor ID Byte 1 0
Summary of the content on the page No. 12
SCPA033 Latency Timer Register (PCI offset 0Dh) – This register indicates the number of PCI clocks the PCI1520 will be allowed access to the PCI bus if another master has its REQ# asserted. The recommended value is 40h. However, the value should be dependent on the system implementation and which devices need priority. CardBus Latency Timer Register (PCI offset 1Bh) – This register indicates the number of CardBus clocks the PCI1520 will be allowed access on the CardBus interface. Because the Car
Summary of the content on the page No. 13
SCPA033 9 Power Management Considerations 9.1 D3 Wake Information A power management event (PME) is the process by which a PCI or CardBus function can request a change of its current power consumption state. Typically, a device uses PME# to request a change from a power savings state to the fully operational state, D0. PME Context is defined as the functional state information and logic required to generate PMEs, report PME status, and enable PMEs. PCI Function Context refers to the small amount
Summary of the content on the page No. 14
SCPA033 9.1.1 GRST# Only Registers Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST# signal is gated only by the SUSPEND# signal. This means that assertion of SUSPEND# blocks the GRST# signal internally, thus preserving all register contents. The registers cleared only by GRST# are: • Status register (PCI offset 06h): bits 15-11, 8 • Secondary status register (PCI offset 16h): bits 15-11, 8 • Interrupt pin register (PCI offset 3Dh):
Summary of the content on the page No. 15
SCPA033 9.1.2 PME# Context Registers If the PME# enable bit (bit 8) of the power-management control/status register (PCI offset A4h) is asserted, then the assertion of PRST# will not clear the following PME# context bits. If the PME# enable bit is not asserted, then the PME# context bits are cleared with PRST#. The PME# context bits are: • Bridge control register (PCI offset 3Eh): bit 6 • System control register (PCI offset 80h): bits 10, 9, 8 • Power-management control/status register (PCI offs
Summary of the content on the page No. 16
SCPA033 STOPCLK – Socket Control Register (CB offset 10h, bit 7). This bit determines whether the CB CLKRUN# protocol is affected by the PCI CLKRUN# protocol. CLKCTRLEN – Socket Power Management Register (CB offset 20h, bit 16). This bit enables the CB CLKRUN# protocol. CLKCTRL – Socket Power Management Register (CB offset 20h, bit 0). This bit determines whether the CB CLKRUN# protocol will either stop or slow CCLK. 9.4 SUSPEND# The assertion of the SUSPEND# signal gates PCLK, GRST#, PRST# from
Summary of the content on the page No. 17
SCPA033 11 Migration to the PCI1520 from the PCI1420 The major differences between the PCI1520 and PCI1420 are pinout, lower power consumption, and lower cost. The pinout is changed on the PCI1520 in order to incorporate an internal voltage regulator which allows the core to operate at 2.5V. When moving from the PCI1225 to the PCI1520, please see Section 13 for the differences between the PCI1225 and PCI1420 in addition to the changes from this section. 11.1 Hardware and Pin Assignment Changes •
Summary of the content on the page No. 18
SCPA033 11.2 Configuration Register Changes • The device ID for the PCI1520 is AC55. • Bit 23 in the System Control register (PCI offset 80h) is reserved on the PCI1520. On the PCI1420, this enabled PCI Bus power management specification revision 1.1 reporting. The PCI1520 is compliant to revision 1.1 by default. • The default value of the Multifunction Routing register (PCI offset 8Ch) has been changed from 00000000h on the PCI1420 to 00001000h in order to enable IRQSER on MFUNC3 by default. •
Summary of the content on the page No. 19
SCPA033 11.3 Other Functional Differences • The PCI1520 is natively supported by Windows XP. The PCI1520 will be recognized natively as a Generic CardBus Controller under Windows 2000, Windows ME, and Windows 98SE. The device will function properly using this driver. However, it is recommended that new drivers provided by Texas Instruments be used for non-XP systems. These drivers have a few small tweaks and allow the device to be reported in Device Manager properly. • The latest version of the
Summary of the content on the page No. 20
SCPA033 12 Migration to the PCI1420 from the PCI1225 The major differences between the PCI1420 and PCI1225 are the ability to wake from the D3 power state and the integration of the pullup resistors on the PC Card interface. This is done using a global reset pin. 12.1 Hardware and Pin Assignment Changes • The pinout changed slightly from the PCI1225 to the PCI1420. A VCC pin has been replaced by a global reset pin (GRST#). This requires a PCB redesign. This pin allows for wake from the D3 power
