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TMS320C6747 DSP
Universal Serial Bus (USB)
OHCI Host Controller
User's Guide
Literature Number: SPRUFM8
September 2008
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2 SPRUFM8–September 2008 Submit Documentation Feedback
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Contents Preface ........................................................................................................................................ 6 1 Introduction......................................................................................................................... 7 1.1 Purpose of the Peripheral................................................................................................ 7 2 Architecture ...............................................................
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www.ti.com List of Figures 1 Relationships Between Virtual Address Physical Address............................................................ 11 2 OHCI Revision Number Register (HCREVISION) ..................................................................... 13 3 HC Operating Mode Register (HCCONTROL) ......................................................................... 13 4 HC Command and Status Register (HCCOMMANDSTATUS)....................................................... 15 5 HC Int
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www.ti.com List of Tables 1 USB Host Controller Registers ........................................................................................... 12 2 OHCI Revision Number Register (HCREVISION) Field Descriptions............................................... 13 3 HC Operating Mode Register (HCCONTROL) Field Descriptions................................................... 14 4 HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions ................................ 15 5 HC Interrup
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Preface SPRUFM8–September 2008 Read This First About This Manual This document describes the universal serial bus OHCI host controller. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the regi
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User's Guide SPRUFM8–September 2008 Universal Serial Bus OHCI Host Controller 1 Introduction This document describes the universal serial bus OHCI host controller. 1.1 Purpose of the Peripheral The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) data rates. It is compatible with the Universal Serial Bus Specification Revision 2.0 and the Open HCI—Open Host C
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Architecture www.ti.com 2 Architecture 2.1 USB1 Module Clock and Reset The USB1 module requires that several different clocks are present before it can be accessed: 1. Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4) 2. Local bus clock to the USB Host controller (derived from SYSCLK4) 3. USB bus side 48-MHz reference clock must be present. Several options are available to source this clock. 2.1.1 Internal System Bus Clocks Needed by the USB1 Module The inter
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www.ti.com Architecture 2.2 USB1 Module Open Host Controller Interface Functionality 2.2.1 OHCI Controller Overview The Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a defines a set of registers and data structures stored in system memory that control how a USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 2.0, defines most of the USB functionality that the USB host controller prov
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Architecture www.ti.com 2.4 Implementation of OHCI Specification for USB 2.4.1 USB Host Controller Endpoint Descriptor (ED) List Head Pointers The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in malfunction. As a specific example, the HCCONTROLHEADED and HCBULKHEADED pointer registers and the 32 HCCAINTERRUPTTABLE pointers must all point to valid phys
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www.ti.com Architecture 2.5 OHCI Interrupts The USB1 host controller can be controlled either by the ARM or the DSP. It has the ability to interrupt either processor. 2.6 USB Host Controller Access to System Memory The USB1 module needs to access system memory to read and write the OHCI data structures and data buffers associated with USB traffic. The switch fabric allows the USB host controller to access system memory, as shown in . 2.7 Physical Addressing Transactions on the internal bus use p
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Registers www.ti.com 3 Registers Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI Specification for USB. Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB host controller state. USB host controller registers can be accessed in user and supervisor modes. To enhance code reusability with possible future versions of the USB host controller, reads and writes to reserved USB host control
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www.ti.com Registers 3.1 OHCI Revision Number Register (HCREVISION) The OHCI revision number register (HCREVISION) is shown in Figure 2 and described in Table 2. Figure 2. OHCI Revision Number Register (HCREVISION) 31 16 Reserved R-0 15 8 7 0 Reserved REV R-0 R-10h LEGEND: R = Read only; -n = value after reset Table 2. OHCI Revision Number Register (HCREVISION) Field Descriptions Bit Field Value Description 31-8 Reserved 0 Reserved 7-0 REV 10h OHCI revision number. 3.2 HC Operating Mode Register
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Registers www.ti.com Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions Bit Field Value Description 31-11 Reserved 0 Reserved 10 RWE 0-1 Remote wake-up enable. 9 RWC 0-1 Remote wake-up connected. 8 IR 0 Interrupt routing. The USB host controller does not provide an SMI interrupt. This bit must be 0 to allow the USB host controller interrupt to propagate to the MPU level 2 interrupt controller. 7-6 HCFS 0-3h Host controller functional state. A transition to USB operational causes
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www.ti.com Registers 3.3 HC Command and Status Register (HCCOMMANDSTATUS) The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table 4. Figure 4. HC Command and Status Register (HCCOMMANDSTATUS) 31 18 17 16 Reserved SOC R-0 R-0 15 4 3 2 1 0 Reserved OCR BLF CLF HCR R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value
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Registers www.ti.com 3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB host controller internal interrupt sources. HCINTERRUPTSTATUS is shown in Figure 5 and described in Table 5. Figure 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) 31 30 29 16 Rsvd OC Reserved R-0 R-0 R-0 15 7 6 5 4 3 2 1 0 Reserved RHSC FNO UE RD SF WDH SO R-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 LEGEND: R
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www.ti.com Registers 3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6. Figure 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) 31 30 29 16 MIE OC Reserved R/W1S-0 R-0 R-0 15 7 6 5 4 3 2 1 0 Reserved RHSC FNO UE RD SF WDH SO R-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R
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Registers www.ti.com 3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7. Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) 31 30 29 16 MIE OC Reserved R/W-0 R-0 R-0 15 7 6 5 4 3 2 1 0 Reserved RHSC FNO UE RD SF WDH SO R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Wri
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www.ti.com Registers 3.7 HC HCAA Address Register (HCHCCA) The HC HCAA address register (HCHCCA) defines the physical address of the beginning of the HCCA. HCHCCA is shown in Figure 8 and described in Table 8. Figure 8. HC HCAA Address Register (HCHCCA) 31 16 HCCA R/W-0 15 8 7 0 HCCA Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. HC HCAA Address Register (HCHCCA) Field Descriptions Bit Field Value Description 31-8 HCCA 0-FF FFFFh Physical address of t
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Registers www.ti.com 3.9 HC Head Control Register (HCCONTROLHEADED) The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10. Figure 10. HC Head Control Register (HCCONTROLHEADED) 31 16 CHED R/W-0 15 4 3 0 CHED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10. HC Head Control Register (HCCONTROLHEADED) Field Des
