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MF1153 03
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CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C63558
Technical Manual
S1C63558 Technical Hardware
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level re
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Revisions and Additions for this manual Chapter Section Page Item Contents 2 2.1.2 8 Table 2.1.2.1 LCD drive voltage when The table was revised. generated internally 4 4.7.3 49 Table 4.7.3.1 LCD drive voltage when The table was revised. generated internally S1C63557 Technical Manual
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The information of the product number change Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 63158 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development
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CONTENTS CONTENTS CHAPTER 1OUTLINE ________________________________________________ 1 1.1 Features ........................................................................................................ 1 1.2 Block Diagram .............................................................................................. 2 1.3 Pin Layout Diagram ..................................................................................... 3 1.4 Pin Description ................................................
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CONTENTS 4.5.3 High impedance control ............................................................................ 34 4.5.4 Special output ............................................................................................ 34 4.5.5 I/O memory of output ports ....................................................................... 37 4.5.6 Programming notes ................................................................................... 40 4.6 I/O Ports (P00–P03, P10–P13, P20–P23 and P
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CONTENTS 4.12.3 Control of buzzer output ......................................................................... 101 4.12.4 Setting of buzzer frequency and sound level.......................................... 102 4.12.5 Digital envelope ..................................................................................... 103 4.12.6 One-shot output ...................................................................................... 104 4.12.7 I/O memory of sound generator ...................
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CONTENTS 7.8 Telephone Function Characteristics ........................................................... 166 7.9 Timing Chart ............................................................................................... 166 7.10 Characteristic Curves (reference value) .................................................... 167 CHAPTER 8PACKAGE _______________________________________________ 169 8.1 Plastic Package.................................................................................
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CHAPTER 1: OUTLINE CHAPTER 1OUTLINE The S1C63558 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM (8,192 words × 13 bits), RAM (5,120 words × 4 bits), serial interface, watchdog timer, program- mable timer, time base counters (2 systems), SVD circuit, a dot-matrix LCD driver that can drive a maximum 40 segments × 17 commons, DTMF/DP generator, FSK demodulator and sound generator built-in. The S1C63558 features high speed operation and low current consumptio
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CHAPTER 1: OUTLINE 1.2 Block Diagram ROM System Reset RESET 8,192 words × 13 bits Control Core CPU S1C63000 OSC1 Interrupt OSC2 OSC Generator OSC3 OSC4 Stopwatch RAM Timer 5,120 words × 4 bits Clock Data ROM Timer 2,048 words × 4 bits Programmable COM0–7 LCD Driver Timer/Counter SEG0–39 40 SEG × 17 COM ∗1 (SEG47–40 ) COM8–16 K00–K03 VDD K10–K13 Input Port VC1–5 Power CA–CC TEST Controller VD1 VSS R00–R03 Output Port R10–R13 R20–R23 SVD SVD Sound TONE Telephone Generator DP Function P00–P03 P10
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CHAPTER 1: OUTLINE 1.3 Pin Layout Diagram QFP15-128pin 96 65 97 64 S1C63558 INDEX 128 33 1 32 No. Pin name No. Pin name No. Pin name No. Pin name 1 N.C. 33 SEG4 65 N.C. 97 N.C. 2 SEG34 34 SEG3 66 R10 98 P00 3 SEG33 35 SEG2 67 R03 99 K13 4 SEG32 36 SEG1 68 R02 100 K12 5 SEG31 37 SEG0 69 R01 101 K11 6 SEG30 38 COM7 70 R00 102 K10 7 SEG29 39 COM6 71 CDIN 103 K03 8 SEG28 40 COM5 72 BPOUT 104 K02 9 SEG27 41 COM4 73 RDRC 105 K01 10 SEG26 42 COM3 74 RDIN 106 K00 11 SEG25 43 COM2 75 VREF 107 SVD 12 SEG2
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CHAPTER 1: OUTLINE 1.4 Pin Description Table 1.4.1 Pin description Pin name Pin No. I/O Function VDD 52 – Power (+) supply pin VSS 46 – Power (–) supply pin VD1 49 – Oscillation system regulated voltage output pin VC1–VC5 108–111 – LCD system power supply pin (1/4 bias generated internally) CA–CC 114–112 – LCD system boosting/reducing capacitor connecting pin OSC1 47 I Crystal oscillation input pin OSC2 48 O Crystal oscillation output pin OSC3 50 I Ceramic oscillation input pin OSC4 51 O Ceram
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CHAPTER 1: OUTLINE 1.5 Mask Option Mask options shown below are provided for the S1C63558. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. The function option generator FOG63558, that has been prepared as the development software tool of S1C63558, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the FOG63558. Refer to the "S5U1C63558D Manual" for the FOG63558.
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CHAPTER 1: OUTLINE (8) Output specification of the DP terminal Either complementary output or N-channel open drain output can be selected as the output specifica- tion for the DP (dial pulse output) terminal. Refer to Section 4.14.2, "Mask option", for details. (9) Gain of FSK demodulator input amplifier The gain of the FSK demodulator input amplifier can be either fixed at 1 using the internal feedback resistor or varied using external resistors. Refer to Section 4.15.2, "Mask option", for deta
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CHAPTER 1: OUTLINE 5. I/O PORT OUTPUT SPECIFICATION • P00 1. Complementary 2. Nch-OpenDrain • P01 1. Complementary 2. Nch-OpenDrain • P02 1. Complementary 2. Nch-OpenDrain • P03 1. Complementary 2. Nch-OpenDrain • P10 1. Complementary 2. Nch-OpenDrain • P11 1. Complementary 2. Nch-OpenDrain • P12 1. Complementary 2. Nch-OpenDrain • P13 1. Complementary 2. Nch-OpenDrain • P20 1. Complementary 2. Nch-OpenDrain • P21 1. Complementary 2. Nc
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2POWER SUPPLY AND INITIAL RESET 2.1 Power Supply The S1C63558 operating power voltage is as follows: Supply voltage VDD = 2.2 V to 5.5 V The S1C63558 operates by applying a single power supply within the above range between VDD and VSS. The S1C63558 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2.1.1. Table 2.1.1 Power supply circuits Circuit Power supply circuit Output
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C63558 circuits, initial reset must be executed. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting) The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the circuits are initialized by only t
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.2 Simultaneous low input to terminals K00–K03 Another way of executing initial reset externally is to input a low signal simultaneously to the input ports (K00–K03) selected with the mask option. Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at low level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal opera- tion. The noise reject circuit does not
