ページ1に含まれる内容の要旨
1
The
bit CPU core,
With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the
an excellent design solution for a wide variety of applications
pins of the 80-pin QFP package can be dedicated to I/O. Six
to internal and external events. In addition, the 's advanced CMOS technology provides for
ing voltage range.
OTP
microcontroller is also available in OTP (One Time Programmable) version,
and in pin configuration.
1- 1
EPROM instead of masked ROM. The KS5
ページ2に含まれる内容の要旨
– × 4-bit RAM – format – 8 K × 8-bit ROM – 16 K × Interrupts I/O Pins – Three internal vectored interrupts – – external vectored interrupts – I/O: 24 pins – – Memory-Mapped I/O Structure – – Maximum 16-digit LCD direct drive capability Two Power-Down Modes – – – Display modes: Static, 1/2 duty (1/2 bias), – Stop mode (main Oscillation Sources – Crystal, ceramic, or RC for main system clock – Programmable interval timer – or external – Watchdog timer – Main system clock frequency: 4.19 MHz (typ
ページ3に含まれる内容の要旨
W W X X IN OUT INT0, INT1,INT2 RESET IN OUT /SO Figure 1 . Simplified Block Diagram 1- 3 KS57C2308/C2316 -1 /SI /SCK P0.3 P0.2 P0.1 Memory Memory Program Data Port 8/16-Kbyte x 4-Bit 512 Serial I/O P3.3 P3.2 SEG24-SEG31 I/O Port 3 I/O Port 8 P3.1/LCDSY P8.0-P8.7/ Pointer P3.0/LCDCK Stack P2.3/BUZ Arithmetic and Logic Unit P2.2/CLO I/O Port 2 KS4-KS7 P2.1 FLAGS I/O Port 7 P7.0-P7.3/ P2.0/TCLO0 KS0-KS3 I/O Port 6 P1.3/TCL0 Instruction Decoder P6.0-P6.3/ Status Word P1.2/INT2 Input Port 1 Program
ページ4に含まれる内容の要旨
SEG2 1 64 SEG19 SEG1 2 63 SEG20 SEG0 3 62 SEG21 4 61 SEG22 5 60 SEG23 6 59 P8.0/SEG24 7 58 P8.1/SEG25 8 57 P8.2/SEG26 9 56 P8.3/SEG27 10 55 P8.4/SEG28 11 54 P8.5/SEG29 KS57C2308 V 12 53 P8.6/SEG30 V KS57C2316 13 52 P8.7/SEG31 X 14 51 P7.3/KS7 (TOP VIEW) X 15 50 P7.2/KS6 IN 16 49 P7.1/KS5 17 48 P7.0/KS4 IN 18 47 P6.3/KS3 RESET 19 46 P6.2/KS2 P0.0/INT4 20 45 P6.1/KS1 21 44 P6.0/KS0 P0.2/SO 22 43 P5.3 P0.3/SI 23 42 P5.2 24 41 P5.1 Figure 1 . - 1- 4 25 80 P1.1/INT
ページ5に含まれる内容の要旨
Table 1 - Pin Descriptions Pin Circuit Type Pin Type I 4-bit input port. * I/O SCK D * I/O SO D I SI I 4-bit input port. I/O 4-bit I/O port. D – BUZ I/O 4-bit I/O port. D Each individual pin can be specified as input – I/O – E * I/O 4-bit I/O ports. Port 6 pins are individually D O Output port for 1-bit data (for use as CMOS driver only) O – O O – V – – – BIAS – 8 – – – I/O D 1- 5 Input P3.0 32 LCD clock output for display expansion LCDCK LCD power control SDAT assignable by mask option are
ページ6に含まれる内容の要旨
Table 1 - Pin Descriptio ns (Continued) Pin Circuit Type Pin Type I/O D I/O E xternal clock input for timer/counter 0 I/ O Timer/counter 0 clock output P D SI I Serial interface * SO I/ O Serial interface D * SCK I/O Serial I/O interface clock signal D I External interrupts . The triggering edge for Only INT0 is I t with detection of rising edge I External interrupt input with detection of rising or falling edge * K S I/O D I/ O C PU c D BUZ I/ O 2, 4, 8 or 16 k D with 4.19 MHz main syste
ページ7に含まれる内容の要旨
V V DD DD P-CHANNEL P-CHANNEL DATA IN OUT N-CHNNEL N-CHANNEL OUTPUT DISABLE Figure 1 . Pin Circuit Type A Figure 1 . Pin Circuit Type C V DD V DD I/O IN Figure 1 . Pin Circuit Type Figure 1 . Pin Circuit Type D (P0.1, P0.2, P2, P3, P6, P7) 1- 7 -6 A-1 (P1, P0.0, P0.3) -4 CIRCUIT TYPE A SCHMITT TRIGGER DISABLE OUTPUT TYPE C CIRCUIT DATA ENABLE ENABLE P-CHANNEL P-CHANNEL RESISTOR RESISTOR RESISTOR RESISTOR PULL-UP PULL-UP -5 -3 PIN CIRCUIT DIAGRAMS PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316
ページ8に含まれる内容の要旨
V DD V DD V DD V P - I/O V LCD SEGMENT/ OUT & PORT 8 DATA Figure 1 . Pin Circuit Type E (P4, P5) V V Figure 1 . Pin Circuit Type V V DD IN V SCHMITT TRIGGER Figure 1 - 1 0 . Pin Circuit Type B ( ) Figure 1 . Pin Circuit Type 1- 8 H-15 (SEG/COM) -8 RESET LC2 COMMON DATA OUT LCD SEGMENT/ LC1 H-16 (P8) -9 LC0 LC2 -7 CIRCUIT TYPE A ENABLE N-CH OUTPUT LC1 CH DATA ENABLE LC0 RESISTOR RESISTOR PNE PULL-UP 16/P2316 KS57C2308/P2308/C23 PRODUCT OVERVIEW
ページ9に含まれる内容の要旨
2 ROM maps for devices are mask programmable at the factory. × 8-bit × 8-bit program memory, aside from the differences in the ROM size onfiguration, the device's 8,192 × 8-bit × 8-bit ) program memory has four — — — — — ) . A 1 2 eir initial value for the REF Instructions Table ROM Area Function B H 1 FFFH 2 - 1 16256 (KS57C2316) 0080H–3FFFH (KS57C2316) 8064 (KS57C2308) (KS57C2308) 0080H– General-purpose program memory 96 0020H–007FH REF instruction look-up table area 20 H–001FH 000C General
ページ10に含まれる内容の要旨
) 1 FFFH ( 3 FFFH ) the ROM. 2 memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. NOTE: microcontroller. VENTn. The programming tips on the 0000H VECTOR ADDRESS AREA 7 6 5 4 3 2 1 0 000BH 0000H 000CH GENERAL-PURPOSE AREA 001FH 0002H INTB/INT4 0020H REFERENCE 0004H AREA INT0 007FH 0080H 0006H INT1 0008H GENERAL-PURPOSE AREA INTS 000AH INTT0 1FFFH 3F FFH Figure . Figure 2 - 2 ROM Address Structure 1. 2- Address Struct
ページ11に含まれる内容の要旨
+ + P ROGRAMMING TIP — Defining Vectored Interrupts areas in program memory: When all vector interrupts are used: ORG ; ← 1, ERB ← 0; Jump to by 0,0,INTB ; EMB ← 0, ERB ← by INTB ; EMB ← 0, ERB ← by INT0 ; EMB ← 0, ERB ← by INT1 0,0,INTS ; EMB ← 0, ERB ← by INTS 0,0,INTT0 ; EMB ← 0, ERB ← by INTT0 When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt ORG ; EMB ← 1, ERB ← 0; Jump to by 0,0,INTB ; EMB ← 0, ERB ← by INTB OR
ページ12に含まれる内容の要旨
1 tion, or in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. execute in — — — + + PROGRAMMING TIP — Using the REF Look-Up Table ORG JMAIN TJP MAIN ; 0, MAIN BTSF KEYFG ; 1, KEYFG CHECK WATCH ; @HL,A ; 3, (HL) ← A • • • ; ← ORG H MAIN • • • REF ; BTSF KEYFG (1-byte instruction) REF JMAIN ; KEYFG = 1, jump to MAIN (1-byte instruction) REF WATCH ; KEYFG = REF ; @HL,A ; REF ; • • • 2 - 4 EA,#00H (1-byte instruction) LD ABC HL INCS LD INCHL CLOCK (1-byte instruction) 0,
ページ13に含まれる内容の要旨
it data memory has four — × — × 4 — × 4 — × 4 -bit area for LCD data in bank 1 — × Initialization values for the data memory area are not defined by hardware and must therefore be initialized by RESET RESET most of 000H WORKING REGISTERS (32 x 4 Bits) 01FH 020H BANK 0 GENERAL-PURPOSE REGISTERS AND STACK AREA (224 x 4 Bits) 0FFH 100H GENERAL-PURPOSE REGISTERS (224 x 4 Bits) BANK 1 1DFH 1E0H LCD DATA REGISTERS (32 x 4 Bits) 1FFH ~ ~ F80H MEMORY-MAPPED I/O BANK 15 AEERESS REGISTERS (128 x
ページ14に含まれる内容の要旨
The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15. When the With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all The RAM working register area in data memory bank 0 is further divided into four indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable 2 - 6 us
ページ15に含まれる内容の要旨
Table Working registers 0 0, 1 0 FH 1 1 1 0, 1 + + PROGRAMMING TIP 1 ; –1FFH) clear @HL,A 0 ; –0FFH) clear @HL,A 2 - 7 RMCL0 JR HL INCS LD RMCL0 HL,#10H LD RAM (010H SMB RMCL1 JR HL INCS LD RMCL1 A,#0H LD HL,#00H LD RAM (100H SMB RAMCLR Clear banks 0 and 1 of the data memory area: — Clearing Data Memory Banks 0 and 1 15 15 I/O-mapped hardware registers F80H–FFFH LCD Data registers 0H–1FFH 1E General-purpose registers 1D 100H– Stack and general-purpose registers 020H–0FFH 000H–01FH SMB Value E
ページ16に含まれる内容の要旨
WORKING REGISTERS A E L H WORKING X W Z Y Figure . 2 - 8 Working Register Map 2-4 01FH BANK 3 ... Y A REGISTER 018H 017H BANK 2 ... Y A REGISTER 010H 00FH BANK 1 ... Y A REGISTER 008H 007H BANK 0 MEMORY 006H DATA 005H BANK 0 REGISTER 004H 003H 002H 001H 000H units or, using paired registers, as 8-bit units. registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-bit intermediate results during program execution, as well as pointer values
ページ17に含まれる内容の要旨
and 3 for interrupt service Table Working Register Organization and Addressing ERB Setting SRB Settings 3 2 1 0 0 0 0 – – 0 0 1 0 0 0 1 1 0 1 1 Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and A, can either be manipulated individually using 4-bit instructions, or together as register pai rs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z
ページ18に含まれる内容の要旨
1- C 4 - A 8 - Figure . Recommendation for Multiple Interrupt Processing from the stack to working memory using the POP instruction. 2 - 10 in the same register bank. When the routines have executed successfully, you can restore the register contents by using the PUSH RR instruction to save register contents to the stack before the service routines are executed If more than four interrupts are being processed at one time, you can avoid possible loss of working register data 1-Bit, 4-Bit, and 8-
ページ19に含まれる内容の要旨
+ + PROGRAMMING TIP — When ERB = "0": ; ← 1, ERB ← ; 2 ; = ; WX ; YZ ; ; 0 WX,EA YZ,EA POP ; POP EA register contents from stack POP YZ ; POP YZ register contents from stack POP WX ; POP WX register contents from st POP ; POP ; POP current SMB, SRB IRET When ERB = "1": ; EMB ← 1, ERB ← ; 2 ; = 0 WX,EA YZ,EA POP ; IRET 2 - 11 Restore SMB, SRB SB LD LD HL INCS HL,#40H LD 80H,EA LD EA,#00H LD SMB "1" use of ERB Select register bank 2 beca SRB Store current SMB, SRB SB PUSH INT0 1, Jump t
ページ20に含まれる内容の要旨
STACK POINTER (SP) ritten by 8 -bit control CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. of the current value of the Since the RESET value of the stack pointer is not defined in firmware, we recommend that you
