ページ1に含まれる内容の要旨
DSCLP-200/300
Two Channel RS-422/485 Asynchronous
Communications Adapter
for PCI bus
User's Manual
QUATECH, INC. TEL: (330) 434-3154
662 Wolf Ledges Parkway FAX: (330) 434-1409
Akron, Ohio 44311 http://www.quatech.com
ページ2に含まれる内容の要旨
? 2002 Quatech, Inc. NOTICE The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice. The authors have taken due care in the preparation of
ページ3に含まれる内容の要旨
WARRANTY INFORMATION Quatech, Inc. warrants the DSCLP-200/300 to be free of defects for five (5) years from the date of purchase. Quatech, Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights. Please complete the following information and retain for yo
ページ4に含まれる内容の要旨
Declaration of Conformity Manufacturer's Name: Quatech Inc. Manufacturer's Address: 662 Wolf Ledges Parkway Akron, Ohio 44311 (USA) Application of Council Directive: 89/336/EEC Standards to which Conformity is Declared: * EN50081-1 (EN55022, EN60555-2, EN60555-3) * EN50082-1 (IEC 801-2, IEC 801-3, & IEC 801-4) Type of Equipment: Information Technology Equipment Equipment Class: Commercial, Residential, & Light Industrial Product Name: PCI Dual Serial Communications Card Model
ページ5に含まれる内容の要旨
Table of Contents 1 General Information ............................................. 1 1.1 Optional Features ................................................. 2 1.1.1 "IND" Option --- Surge Suppression Upgrade ................. 2 1.1.2 "750" Option --- UART Upgrade ............................ 2 2 Hardware Configuration ........................................ 3 2.1 RS-422 or RS-485 Signal Line Termination .......................... 3 2.2 Signal Connections ....................................
ページ6に含まれる内容の要旨
1 General Information The Quatech, Inc. DSCLP-200/300(two-port) and SSCLP-200/300 (one-port) provides upto provides two RS-422 or RS-485 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the PCI expansion bus. The DSCLP-200/300 uses Quatech's new Enhanced Serial Adapter design. Legacy serial port data rates are limited to a maximum of 115,200 bits per second. Quatech Enhanced Serial Adapters can achieve data rates as high as 460,800 bits per secon
ページ7に含まれる内容の要旨
2 Hardware Configuration The DSCLP-200/300 is automatically configured at boot time by the computer's BIOS or operating system. There are no required switches or jumpers to set for installation. This chapter lists a number of jumper settings that control various hardware features. Jumpers J1-J4, located in a column near the D-9 connectors, control the RS-422 or RS-485 signal line termination. Jumpers J5-J8, located in a column just to the right of J1-J4, control how signals are routed from
ページ8に含まれる内容の要旨
2.2 Signal Connections The DSCLP-200/300 provides each of two serial ports with four differential signal pairs: TxD, RxD, AUXOUT, and AUXIN. TxD and RxD are always present at the connector. The AUXOUT and AUXIN signals can be used to support RTS/CTS handshaking, external clocking, or external signal loopback. The factory default configuration, as shown in Figure 2, is a loopback of AUXOUT to AUXIN at the connector, with RTS and CTS looped back on the board. There is an extensive discussion
ページ9に含まれる内容の要旨
J2 SPAD X4 J4 X2 J5 J10 CTS0_SEL J11 AUX0_SEL0 AUX0_SEL1 J12 J13 RCLK0_SEL TGL0_SEL0 J14 J15 TGL0_SEL1 J16 RXEN0_SEL CTS1_SEL J17 J18 AUX1_SEL0 J19 AUX1_SEL1 J20 RCLK1_SEL TGL1_SEL0 J21 J22 TGL1_SEL1 J23 RXEN1_SEL Right Card Edge Jumpers 2.3.1 CTS0_SEL, CTS1_SEL (J10,17) With NO jumpers on J10 or J17 the mode selection is CTS=AUXIN. With Jumpers installed the mode selection is CTS=RTS. 2.3.2 AUX0_SEL1,0, AUX1_SEL1,0 (J12,11,19,18) With NO jumpers on J12 or J19 the mode selection is AUXOUT=RTS.
ページ10に含まれる内容の要旨
With NO jumpers on J13 or J20 the mode selection is RCLK=TCLK. With Jumpers installed on J13 or J20 the mode selection is RCLK=AUXIN. 2.3.4 TGL0_SEL1,0, TGL1_SEL1,0 (J15,14,22,21) With NO jumpers on J15,14, or J22,21 the mode selection is TXEN=1. With Jumpers installed on J14 or J21 and NO jumpers on J15 or J22, the mode selection is TXEN=DTR. With Jumpers installed on J15 or J22 and NO jumpers on J14 or J21, the mode selection is TXEN=RTS. With Jumpers installed on J15, J14 or J22, J21,
ページ11に含まれる内容の要旨
J2 SPAD X4 J4 J5 X2 Figure 4 --- Enable scratchpad registers 2.4.2 Force High-Speed UART Clock (X2 or X4, J4-J5) These jumpers force an increase of the UART input clock frequency by a factor of two, four, or eight. This feature can allow legacy software to use baud rates above 115,200 bits per second. It is also useful if the serial port device driver does not directly support setting the higher baud rates through the Options Register (see page 10). If one of these jumpers is applied, it overr
ページ12に含まれる内容の要旨
J2 SPAD X4 J4 J5 X2 X4 mode J2 SPAD X4 J4 J5 X2 X2 mode DSCLP-200/300 User's Manual 7
ページ13に含まれる内容の要旨
3 Hardware Installation 1. Turn off the power of the computer system in which the DSCLP-200/300 is to be installed. 2. Remove the system cover according to the instructions provided by the computer manufacturer. 3. Make any desired optional jumper setting changes. 4. Install the DSCLP-200/300 in any empty PCI expansion slot. The board should be secured by installing the Option Retaining Bracket (ORB) screw. 5. Replace the system cover according to the instructions provided by the computer ma
ページ14に含まれる内容の要旨
4 Address Map and Special Registers This chapter explains how the two UARTs and special registers are addressed, as well as the layout of those registers. This material will be of interest to programmers writing driver software for the DSCLP-200/300. 4.1 Base Address and Interrupt Level (IRQ) The base address and IRQ used by the DSCLP-200/300 are determined by the BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The two ports reside in a single block of I/O space i
ページ15に含まれる内容の要旨
4.2 Enabling the Special Registers The DSCLP-200/300 contains two unique registers, an Interrupt Status Register and an Options Register. These registers are enabled when the SPAD jumper (J13) is removed (factory default). They replace the UART Scratchpad Register on accesses to register address 7. The Interrupt Status Register and Options Register are accessed through the scratchpad location of any UART. The DLAB bit of the UART (Line Control Register, bit 7) is used to select between the t
ページ16に含まれる内容の要旨
4.4 Quatech Modem Control Register The Quatech Modem Control Register can be used to setup each port. To access QMCR write a 0xBF to the LCR(base + 3) and a 0x10 to the Opt Reg(base+7). This will allow the user read/write access to QMCR. The QMCR of the entire DSCLP-200/300, as shown in Figure 9a. The individual bits are cleared as the interrupting ports are serviced. The QMCR will need to be written to after the setup by writing a 0x00 to (base+B). Bit Description 7 (MSB) 0 (always 0) 6 0 (
ページ17に含まれる内容の要旨
4.5 Options Register The Options Register allows software to identify the DSCLP-200/300 as a Quatech Enhanced Serial Adapter. It also allows software to set the UART clock rate multiplier. Figure 10 shows the structure of the Options Register. The powerup default of the Options Register is all bits zero. Bit Name Description 7 (MSB) ID1 ID bit 1 6 ID0 ID bit 0 5 - (reserved, 0) 4 - (reserved, 0) 3 - (reserved, 0) 2 - (reserved, 0) 1 RR1 Clock rate multiplier bit 1 0 RR0 Clock rate multiplier b
ページ18に含まれる内容の要旨
4.5.2 Clock Rate Multiplier A standard serial port operates at a clock speed of 1.8432 MHz. In order to achieve higher data rates, Quatech Enhanced Serial Adapters can operate at two times or four times this standard clock speed. This is controlled by the clock rate multiplier bits in the Options Register. Software can determine the UART clock frequency by reading the clock rate multiplier bits RR1 and RR0 in the Options Register as shown in Figure 12. RR1 and RR0 can be set by writing to the
ページ19に含まれる内容の要旨
5 Windows Configurations 5.1 Windows Millennium 1. After inserting the DSCLP-200/300 for the first time the "Add New Hardware Wizard" will begin. Select "Search for the best driver for your device.". Check the "Removable media" and "Specify location" box. Click the "Next" button. 3. Window will locate the proper INF file and copy the file from the CD. Click the "Next" button. 4. The final dialog screen will verify the file copy from the CD. Click the "Finish" button. 14 DSC
ページ20に含まれる内容の要旨
5.2 Windows 2000 1. After inserting a DSCLP-200/300 for the first time, the "Add New Hardware Wizard will appear at start up. Click the "OK" button. 2. The following dialog box insert the Quatech COM CD (shipped with the device). Click the "OK" button. 4. The following dialog box will display the appropriate INF file on the CD in drive. Click the "OK" button. 5. Window will copy the INF file from the CD and display a final dialog indication that the process is
