ページ1に含まれる内容の要旨
_ V1.1
POD Hardware Reference
Motorola 68HC08LD POD rev. B
Ordering code IC20187
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ページ2に含まれる内容の要旨
_ POD Hardware Reference In-Circuit Emulation PODs The following elements of interest are located on all In-Circuit emulation PODs: • emulation CPU - acts on behalf of target's CPU. On some PODs you must use the same CPU on the POD as it is used on the target (see your POD reference page). In such cases, remove the CPU from the POD and insert the CPU that you use in the target system, in its place. • red LED (D3) - lit when CPU is running • green LED (D4) - lit when Emulator is ready fo
ページ3に含まれる内容の要旨
For every POD the following information is given: • Ordering code. If there are different speed versions of a POD the ordering code is modified by appending the speed in MHz (IC81020-16 for the 16 MHz 8031 POD) • information on available speed versions and required Emulator access time • POD size and position of PIN1 on the target adapter relative to bottom left corner. The memory range specifies the range of addresses that a POD can address. If this specification is omitted the default 1MB is a
ページ4に含まれる内容の要旨
_ POD Hardware Reference Motorola 68HC08LD POD rev. B Ordering code IC20187 Maximum CPU Clock (MHz) 6 Emulator Speed (ns) 65 Exchange CPU NO Before connecting the POD, make sure you have read the technical notes on Motorola 68HC08 Family in the Hardware User's Guide. Top board iSYSTEM, March 2004 4/12
ページ5に含まれる内容の要旨
Bottom board Emulated CPU 68HC908LD64 CPU Mask Information A standard 68HC908LD64 CPU is inserted in the POD. If you are confronted with an unexpected application behaviour, which could be due to a different CPU mask being used in the POD and in the target, feel free to exchange the inserted CPU with the one being used in the target. Contact the CPU vendor for more details on the CPU mask differences. iSYSTEM, March 2004 5/12
ページ6に含まれる内容の要旨
Electrical and Logical Differences In order to enable emulation, 1k Pull-up resistor is present on the Target Reset line. The original ports A and B are used for the emulation and are rebuilt by the port replacement unit on the POD; therefore electrical characteristics are changed. The IRQ line is also used to start the emulation mode of the CPU. During the execution of the user program a 220E resistor and an 100nF capacitor are present on the line, which causes RC delays on this pin. The Analog
ページ7に含まれる内容の要旨
Voltage settings J1 (on the top board) Jumper selector J1 on the top board determines the operational voltage. Position Vcc level Set (*) 5.0 V Removed 3.3 V Jumper J1 settings (* - factory default) This jumper must be set in any way regardless if the power supply is set to Emulator or to Target. Ports Original ports A and B are used for emulation and rebuilt by a port replacement unit. Therefore, electrical characteristics are changed. Because of different technology used in the original chip a
ページ8に含まれる内容の要旨
General HC08 Emulation Notes Internal RAM, Internal EEPROM Note that the internal RAM of the 68HC08 CPU on the POD is disabled during the emulation. Thereby, associated memory area must be mapped as emulator RAM by the user. If the CPU provides a capability to write to the internal RAM or EEPROM via memory window (no specific programming sequence required), the download file can be loaded to the internal RAM or EEPROM using the ‘Target Download’ option. The debugger downloads the code to the int
ページ9に含まれる内容の要旨
The Signal Connector A signal connector is present on this pod, marked as ST4. Pin Signal Description 1 GND Ground 2 BPEXT External Breakpoint 3 RESO Reset Output 4 TRES Target Reset 5 AUX0 Auxilliary Signal Input 6 AUX1 Auxilliary Signal Input 7 AUX2 Auxilliary Signal Input 8 AUX3 Auxilliary Signal Input ST4 Connector signals Target Adapters iSYSTEM offers various adapter solutions for this POD. Please refer to the adapter documentation for more details. iSYSTEM, March 2004 9/12
ページ10に含まれる内容の要旨
POD Target Layout The POD Target Layout is T_QFP64. 15 13 11 9 7 5 3 1 16 14 12 10 8 6 4 2 17 18 64 63 19 20 62 61 21 22 60 59 23 24 58 57 25 26 56 55 27 28 54 53 29 30 52 51 31 32 50 49 34 36 38 40 42 44 46 48 33 35 37 39 41 43 45 47 T_QFP64 – Bottom POD View T_QFP64 – Dimensions (Top View) iSYSTEM, March 2004 10/12
ページ11に含まれる内容の要旨
Notes: iSYSTEM, March 2004 11/12
ページ12に含まれる内容の要旨
Notes: iSYSTEM, March 2004 12/12
