ページ1に含まれる内容の要旨
CY7C1318CV18
CY7C1320CV18
18-Mbit DDR II SRAM 2-Word
Burst Architecture
Features Functional Description
■ 18-Mbit Density (1M x 18, 512K x 36) The CY7C1318CV18, and CY7C1320CV18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR II archi-
■ 267 MHz Clock for high Bandwidth
tecture. The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a one-bit burst counter.
■ 2-word Burst for reducing Address Bus Frequency
Addresses for read and write are latched on altern
ページ2に含まれる内容の要旨
512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array CY7C1318CV18 CY7C1320CV18 Logic Block Diagram (CY7C1318CV18) Burst A0 Logic Write Write 20 19 A Reg Reg (19:0) A Address (19:1) Register 18 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 36 CQ V 18 REF 18 Reg. Reg. Control CQ R/W Logic 18 18 BWS [1:0] Reg. 18 DQ [17:0] Logic Block Diagram (CY7C1320CV18) Burst A0 Logic Write Write 19 18 A Reg Reg (18:0) A Address (18:1) Register 36 LD K Output CLK R/W K Logic Gen. C
ページ3に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Pin Configuration [1] The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1318CV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS K NC/144M LD A NC/36M CQ 1 B NC DQ9 NC A NC/288M K BWS ANC NC DQ8 0 C NC NC NC V AA0A V NC DQ7 NC SS SS D NC NC DQ10 V V V V V NC NC NC SS SS SS SS SS E NC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ F NC DQ12 NC V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC NC DQ13 V V V V V NC
ページ4に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Pin Definitions Pin Name I/O Pin Description DQ Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q are automatically tristated. [x:0] CY7C1318CV
ページ5に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Pin Definitions (continued) Pin Name I/O Pin Description DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I mode when the DLL is turned off. In this mode, the device can be operated at a frequ
ページ6に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 ) the infor- subsequent rising edge of the negative input clock (K Functional Overview mation presented to D is also stored into the write data [17:0] register, provided BWS are both asserted active. The 36 bits The CY7C1318CV18, and CY7C1320CV18 are synchronous [1:0] of data are then written into the memory array at the specified pipelined Burst SRAMs equipped with a DDR interface, which location. Write accesses can be initiated on every rising edge of operates with a
ページ7に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Programmable Impedance DLL An external resistor, RQ, must be connected between the ZQ pin These chips use a Delay Lock Loop (DLL) that is designed to on the SRAM and V to enable the SRAM to adjust its output function between 120 MHz and the specified maximum clock SS driver impedance. The value of RQ must be 5x the value of the frequency. During power up, when the DOFF is tied HIGH, the intended line impedance driven by the SRAM. The allowable DLL is locked after 1024
ページ8に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Truth Table [2, 3, 4, 5, 6, 7] The truth table for the CY7C1318CV18, and CY7C1320CV18 follows. Operation K LD R/W DQ DQ Write Cycle: L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP: No Operation L-H H X High-Z High-Z Standby: Clock Stop
ページ9に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1320CV18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. LLLL – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device.
ページ10に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 13. Upon power up, the instructio
ページ11に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP controller enters the Shif
ページ12に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07160 Rev. *F Page 12 of 26 [+] Feedba
ページ13に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH V Output LOW Voltage I = 2.0
ページ14に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture Hold after Clock Rise 5 n
ページ15に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Identification Register Definitions Value Instruction Field Description CY7C1318CV18 CY7C1320CV18 Revision Number (31:29) 000 000 Version number. Cypress Device ID (28:12) 11010100010010101 11010100010100101 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32
ページ16に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P29 9G 57 5B85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N32 9F 60 5C88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 11C 71 1D 99 2P 16 9N 44 9B
ページ17に含まれる内容の要旨
~ ~ CY7C1318CV18 CY7C1320CV18 DLL Constraints Power Up Sequence in DDR II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF either HIGH or LOW (all other D
ページ18に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the Test Parameter Description Typ Max* Unit Conditions device. These user guidelines are not tested. LSBU Logical 25°C 320 368 FIT/ Storage Temperature ................................. –65°C to +150°C Single-Bit Mb Ambient Temperature with Power Applied.. –55°C to +125°C Upsets Supply Voltage on V Relative to GND ........–0.5V to +2.9V DD LMBU Logical 25°C 0 0.01 FIT/
ページ19に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Electrical Characteristics (continued) DC Electrical Characteristics [12] Over the Operating Range Parameter Description Test Conditions Min Typ Max Unit I Automatic Power Down Max V , 267 MHz (x18) 315 mA SB1 DD Current Both Ports Deselected, (x36) 330 V ≥ V or V ≤ V IN IH IN IL 250 MHz (x18) 300 f = f = 1/t , MAX CYC (x36) 320 Inputs Static 200 MHz (x18) 290 (x36) 300 167 MHz (x18) 285 (x36) 295 AC Electrical Characteristics [11] Over the Operating Range Paramet
ページ20に含まれる内容の要旨
CY7C1318CV18 CY7C1320CV18 Switching Characteristics [20, 21] Over the Operating Range 267 MHz 250 MHz 200 MHz 167 MHz Cypress Consortium Description Unit Parameter Parameter Min Max Min Max Min Max Min Max [22] t V (Typical) to the First Access 1– 1–1 –1– ms POWER DD t t K Clock and C Clock Cycle Time 3.75 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns CYC KHKH t Input Clock (K/K and C/C) HIGH 1.5 – 1.6 – 2.0 – 2.4 – ns t KH KHKL t t Input Clock (K/K and C/C) LOW 1.5 – 1.6 – 2.0 – 2.4 – ns KL KLKH t t K Clock
