ページ1に含まれる内容の要旨
CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
[1]
Features
Functional Description
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined
■ Fully registered inputs and outputs for pipelined operation
SRAM designed to support zero-wait-state secondary cache
■ 128K x 36 common IO architecture
with minimal glue logic. CY7C1347G IO pins can operate at
either the 2.5V or the 3.3V level. The IO pins are 3.3V tolerant
■ 3.3V core power supply (V )
DD
when V = 2.5V. All synchronous inputs pass t
ページ2に含まれる内容の要旨
CY7C1347G Block Diagram A 0, A1, A ADDRESS REGISTER 2 A [1:0] MODE Q1 ADV BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC,DQP C DQC,DQP C BYTE BYTE BW C OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQB,DQP B E DQB,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA,DQP A DQA,DQP A BYTE BW A BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED
ページ3に含まれる内容の要旨
CY7C1347G Pinouts Figure 1. 100-Pin TQFP DQP C 1 80 DQP B DQ C 2 79 DQ B DQ DQ C 3 78 B V DDQ 4 77 V DDQ V SSQ 5 76 V SSQ DQ C 6 75 DQ B DQ BYTE C BYTE B C 7 74 DQ B DQ C DQ 8 73 B DQ C 9 72 DQ B V SSQ 10 71 V SSQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ C 13 68 DQ B NC CY7C1347G V 14 67 SS V DD 15 66 NC NC V 16 65 DD V SS 17 64 ZZ DQ D 18 63 DQ A DQ D DQ 19 62 A V DDQ 20 61 V DDQ V SSQ 21 60 V SSQ DQ DQ D 22 59 A DQ D 23 58 DQ A DQ BYTE D D DQ BYTE A 24 57 A DQ D 25 56 DQ A V SSQ 26 55 V SSQ V
ページ4に含まれる内容の要旨
CY7C1347G Pinouts (continued) Figure 2. 119-Ball BGA 2 1 34 5 6 7 A V AA ADSP A A A V DDQ DDQ NC/288M CE A ADSC A CE NC/576M B 2 3 C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B V DQ V V DQ V F DDQ C SS OE SS B DDQ DQ DQ DQ DQ G BW BW ADV C C B B B C H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D D A A A V DQ V BWE V DQ V M DDQ D SS SS A DDQ DQ DQ V A1
ページ5に含まれる内容の要旨
CY7C1347G Table 1. Pin Definitions Name IO Description A ,A ,A Input- Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge 0 1 Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A feeds 1 2 3 [1:0] the 2-bit counter. BW BW Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. A, B, BW BW Synchronous Sampled on the rising edge of CLK. C, D GW Input- Global Write E
ページ6に含まれる内容の要旨
CY7C1347G described in Table 6 on page 8. Asserting the Byte Write Enable Functional Overview input (BWE) with the selected Byte Write (BW ) input selec- [A:D] tively writes to only the desired bytes. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output Bytes not selected during a byte write operation remain registers controlled by the rising edge of the clock. Maximum unaltered. A synchronous self-timed write mec
ページ7に含まれる内容の要旨
CY7C1347G Table 2. Interleaved Burst Sequence Table 3. Linear Burst Sequence First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A A A A A A A A [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Table 4. ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit I Snooze mode standby current ZZ > V − 0.2V 40
ページ8に含まれる内容の要旨
CY7C1347G [2, 3, 4, 5, 6] Table 5. Truth Table (continued) Add. Next Cycle CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Used Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State Wri
ページ9に含まれる内容の要旨
CY7C1347G Maximum Ratings Exceeding the maximum ratings may shorten the battery life of Current into Outputs (LOW)......................................... 20 mA the device. User guidelines are not tested. Static Discharge Voltage.......................................... > 2001V Storage Temperature ..................................... −65°C to +150°C (MIL-STD-883, Method 3015) Ambient Temperature with Latch-Up Current................................................... > 200 mA Power Applied.
ページ10に含まれる内容の要旨
CY7C1347G Electrical Characteristics (continued) [8, 9] Over the Operating Range Parameter Description Test Conditions Min Max Unit I Automatic CE Max. V , Device Deselected, or 4 ns cycle, 250 MHz 105 mA SB3 DD Power Down V < 0.3V or V > V – 0.3V IN IN DDQ 5 ns cycle, 200 MHz 95 mA Current—CMOS Inputs f = f = 1/t MAX CYC 6 ns cycle, 166 MHz 85 mA 7.5 ns cycle, 133 MHz 75 mA I Automatic CE Max. V , Device Deselected, 45 mA SB4 DD Power Down V ≥ V or V ≤ V , f = 0 IN IH IN IL Current—TTL Input
ページ11に含まれる内容の要旨
CY7C1347G Switching Characteristics [14, 15] Over the Operating Range –250 –200 –166 –133 Parameter Description Unit Min Max Min Max Min Max Min Max [10] t 11 1 1 ms POWER V (Typical) to the first Access DD Clock t Clock Cycle Time 4.0 5.0 6.0 7.5 ns CYC t Clock HIGH 1.7 2.0 2.5 3.0 ns CH t Clock LOW 1.7 2.0 2.5 3.0 ns CL Output Times t Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns CO t Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns DOH [11, 12, 13] t 00 0 0 ns CLZ Clock to Low-Z [
ページ12に含まれる内容の要旨
CY7C1347G Switching Waveforms [16] Figure 5. Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BW [A:D] Deselect t t CEH CES cycle CE t t ADVH ADVS ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) High-Z t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Not
ページ13に含まれる内容の要旨
CY7C1347G Switching Waveforms (continued) [16, 17] Figure 6. Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADS ADH t t ADS ADH ADSC t t AH AS ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A :B] t t WEH WES GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t DS DH Data In (D) D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z t OEHZ Data Out (Q) BURST RE
ページ14に含まれる内容の要旨
CY7C1347G Switching Waveforms (continued) [16, 18, 19] Figure 7. Read/Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CEH CES CE ADV OE t t t DH CO DS t OELZ Data In (D) High-Z D(A3) D(A5) D(A6) t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes 18. The data bus (Q) remains in High-Z following a write
ページ15に含まれる内容の要旨
CY7C1347G Switching Waveforms (continued) [20, 21] Figure 8. ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI A LL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 20. Device must be deselected when entering ZZ mode. See Table 5 on page 7 for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05516 Rev. *F Page 15 of 22 [+] Feedback
ページ16に含まれる内容の要旨
CY7C1347G Ordering Information The following table lists all possible speed, package and temperature range options supported for these devices. Note that some options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative for the status of availability of parts. Cypress maintains a worldwide net
ページ17に含まれる内容の要旨
CY7C1347G Table 7. Ordering Information (continued) Speed Package Operating Ordering Code Package Type (MHz) Diagram Range 250 CY7C1347G-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1347G-250BGC 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1347G-250BGXC 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free CY7C1347G-250BZC 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1347G-250BZXC 165-Ball Fine-Pitch Ball Grid Array
ページ18に含まれる内容の要旨
CY7C1347G Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. B
ページ19に含まれる内容の要旨
CY7C1347G Package Diagrams (continued) Figure 10. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115 51-85115 *B Document #: 38-05516 Rev. *F Page 19 of 22 [+] Feedback
ページ20に含まれる内容の要旨
CY7C1347G Package Diagrams (continued) Figure 11. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER -0.06 Ø0.50 (165X) +0.14 1 2 3 4 5 67 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R A A 1.00 5.00 10.00 B 13.00±0.10 B 13.00±0.10 0.15(4X) NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE COD
