ページ1に含まれる内容の要旨
CY7C1019D
1-Mbit (128K x 8) Static RAM
[1]
Features Functional Description
• Pin- and function-compatible with CY7C1019B The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
• High speed
expansion is provided by an active LOW Chip Enable (CE), an
—t = 10 ns
AA
active LOW Output Enable (OE), and tri-state drivers. This
• Low active power
device has an automatic power-down feature that significantly
reduces power consumption when deselected. The e
ページ2に含まれる内容の要旨
CY7C1019D Pin Configuration SOJ/TSOPII Top View A 1 32 A 0 16 A 1 31 A 2 15 A 30 3 2 A 14 A 3 4 29 A 13 28 CE 5 OE 27 IO 6 0 IO 7 26 IO IO 7 1 6 25 V 8 V CC SS V 24 SS 9 V CC 23 IO IO 2 10 5 IO 22 IO 3 11 4 A 21 WE 12 12 A A 4 11 13 20 A A 5 19 10 14 A A 6 15 18 9 A A 17 16 8 7 Selection Guide –10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Document #: 38-05464 Rev. *E Page 2 of 11 [+] Feedback
ページ3に含まれる内容の要旨
CY7C1019D Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2001V Exceeding the maximum ratings may impair the useful life of (per MIL-STD-883, Method 3015) the device. These user guidelines are not tested. Latch-up Current .................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Ambient Temperature with Operating
ページ4に含まれる内容の要旨
CY7C1019D [3] Capacitance Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, V = 5.0V 6 pF IN A CC C Output Capacitance 8 pF OUT [3] Thermal Resistance 400-Mil Parameter Description Test Conditions TSOP II Unit Wide SOJ Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 56.29 62.22 °C/W JA (Junction to Ambient) four-layer printed circuit board Θ Thermal Resistance 38.14 21.43 °C/W JC (Junction to Case) [4] AC Test Loads and Waveforms ALL INPUT PU
ページ5に含まれる内容の要旨
CY7C1019D [5] Switching Characteristics (Over the Operating Range) –10 (Industrial) Parameter Description Unit Min Max Read Cycle [6] t V (typical) to the first access 100 µs power CC t Read Cycle Time 10 ns RC t Address to Data Valid 10 ns AA t Data Hold from Address Change 3 ns OHA t CE LOW to Data Valid 10 ns ACE t OE LOW to Data Valid 5 ns DOE t OE LOW to Low Z 0 ns LZOE [7, 8] t OE HIGH to High Z 5ns HZOE [8] t CE LOW to Low Z 3ns LZCE [7, 8] t CE HIGH to High Z 5ns HZCE [9] t CE LOW to Pow
ページ6に含まれる内容の要旨
CY7C1019D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min Max Unit V V for Data Retention 2.0 V DR CC I Data Retention Current V = V = 2.0V, CE > V – 0.3V, 3mA CCDR CC DR CC V > V – 0.3V or V < 0.3V IN CC IN [3] t Chip Deselect to Data Retention Time 0 ns CDR [12] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE 4.5V 4.5V V V > 2V DR CC t t CDR R CE Switching Waveforms [13, 14] Read Cycle No. 1 (Address Transition Co
ページ7に含まれる内容の要旨
CY7C1019D Switching Waveforms (continued) [16, 17] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t SCE t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [16, 17] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t t SD HD DATA VALID DATA IO IN NOTE 18 t HZOE Notes 16. Data IO is high impedance if OE = V . IH 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this pe
ページ8に含まれる内容の要旨
CY7C1019D Switching Waveforms (continued) [11, 17] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD DATA IO NOTE 18 DATA VALID t t LZWE HZWE Truth Table CE OE WE IO –IO Mode Power 0 7 H X X High Z Power-Down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Active (I ) CC L H H High Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 10 CY7C10
ページ9に含まれる内容の要旨
CY7C1019D Package Diagrams Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033-*B Document #: 38-05464 Rev. *E Page 9 of 11 [+] Feedback
ページ10に含まれる内容の要旨
CY7C1019D Package Diagrams (continued) Figure 2. 32-pin Thin Small Outline Package Type II (51-85095) 51-85095-** All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05464 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodie
ページ11に含まれる内容の要旨
CY7C1019D Document History Page Document Title: CY7C1019D, 1-Mbit (128K x 8) Static RAM Document Number: 38-05464 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the Ordering Information *B 262950 See ECN RKF Added T Spec in Switching Characteristics table power Added Data Retention Characteristics table and waveforms Sh
