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AMD Geode™ SC3200 Processor
Data Book
February 2007
Publication ID: 32581C
AMD Geode™ SC3200 Processor Data Book
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© 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
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Contents 32581C Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . .
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32581C Contents 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.2 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 32581C List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3-2. BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 4-1. WATCHDOG Block
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32581C List of Figures Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers . . . . . . . . . . . . . . . 316 Figure 7-7. Video Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Figure 7-8. Horizontal Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Figure 7-9. Linear Interpolation Calculation . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 32581C Figure 9-47. AC97 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Figure 9-48. AC97 Sync Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Figure 9-49. AC97 Clocks Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Figure 9-50. AC97 Data TIming Diagram . . . . . . . .
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32581C List of Figures 8 AMD Geode™ SC3200 Processor Data Book
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List of Tables 32581C List of Tables Table 2-1. SC3200 Memory Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC3200 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 3-1. Signal Definitions Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number . .
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32581C List of Tables Table 5-29. Banks 0 and 1 - Common Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 117 Table 5-31. ACB Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 5-32. ACB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables 32581C Table 6-22. F3: PCI Header Registers for Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 6-23. F3BAR0: Audio Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary . . . . . . . . . . . . . . . . . . 183 Table 6-25. F5BAR0: I/O Control Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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32581C List of Tables Table 9-19. PCI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Table 9-20. Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Table 9-21. Sub-ISA Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Table 9-22. LPC and SERIRQ Timing Parameters . . . . . . . . .
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Overview 32581C 1.0Overview 1 1.1 General Description The AMD Geode™ SC3200 processor is a member of the � The Core Logic module includes: PC/AT functionality, a AMD Geode family of fully integrated x86 system chips. USB interface, an IDE interface, a PCI bus interface, an The SC3200 processor includes: LPC bus interface, Advanced Configuration Power Inter- face (ACPI) version 1.0 compliant power management, � The AMD Geode GX1 processor module combines and an audio codec interface. advanced
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32581C Overview 1.2 Features General Features Video Processor Module ■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc- ■ Video Accelerator: tion set support — Flexible video scaling support of up to 800% (horizontally and vertically) ■ Memory controller with 64-bit SDRAM interface — Bilinear interpolation filters (with two taps, and eight ■ 2D graphics accelerator phases) to smooth output video ■ Video/Graphics Mixer: ■ CCIR-656 video input port with direct video for full — 8-bit value
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Overview 32581C ■ PCI Bus Interface: Other Features — PCI v2.1 compliant with wakeup capability ■ High-Resolution Timer: — 32-Bit data path, up to 33 MHz — 32-Bit counter with 1 μs count interval — Glueless interface for an external PCI device — Fixed priority ■ WATCHDOG Timer: — 3.3V signal support only — Interfaces to INTR, SMI, Reset ■ Sub-ISA Bus Interface: ■ Clocks: — Up to 16 MB addressing — Input (external crystals): — Supports a chip select for ROM or Flash EPROM – 32.768 KHz (internal c
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32581C Overview 16 AMD Geode™ SC3200 Processor Data Book
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Architecture Overview 32581C 2.0Architecture Overview 2 As illustrated in Figure 1-1 on page 13, the SC3200 pro- The SC3200 processor’s device ID is contained in the GX1 cessor contains the following modules in one integrated module. Software can detect the revision by reading the device: DIR0 and DIR1 Configuration registers (see Configuration registers in the AMD Geode™ GX1 Processor Data Book). � GX1 Module: The AMD Geode™ SC3200 Specification Update docu- — Combines advanced CPU performance
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32581C Architecture Overview Table 2-1. SC3200 Memory Controller Register Summary GX_BASE+ Width Memory Offset (Bits) Type Name/Function Reset Value 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C0040h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2 00000801h 8408h-840Bh 32 R/W MC_BANK_CFG. Memory Controller Bank Configuration 41104110h 840Ch-840Fh 32 R/W MC_SYNC_TIM1. Memory Controller Synchronous Timing 2A733225h Register 1 8414h-8417h 32 R/W
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Architecture Overview 32581C Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description 4 RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin is enabled, processor, graphics pipeline, and low priority display con- troller requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority level. High priority
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32581C Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 only) 1: 2 Module banks (Bank 0 and 1) 13 RSVD (Reserved). Write as 0. 12 SODIMM_COMP_BNK (SODIMM Component Banks - Ba
