ページ1に含まれる内容の要旨
Powerful Energy Meter Chipset
ADSST-SALEM-3T
chipset can be interfaced to any general-purpose microproces-
FEATURES
sor to develop state of the art tri-vector or polyphase energy
High accuracy
metering solutions with a wide range of basic currents from 1 A
Supports IEC 60687/61036 and ANSI C12.1/12.20
to 30 A. By incorporating a comprehensive data set of parame-
Suitable for class0.5 and class0.2 meter
ters, including instantaneous measurements, accumulated
Full four quadrant me
ページ2に含まれる内容の要旨
ADSST-SALEM-3T TABLE OF CONTENTS Easy Calibration............................................................................ 3 General Description of the ADSST-73360LAR ADC................ 11 Specifications—ADSST-73360LAR ............................................. 12 Effective Phase Compensation ................................................... 3 Absolute Maximum Ratings—ADSST-73360LAR .................... 14 Ease of Design...........................................................
ページ3に含まれる内容の要旨
ADSST-SALEM-3T EASY CALIBRATION EASE OF DESIGN The ADSST-SALEM-3T chipset has highly advanced calibration Designing a complete meter using the ADSST-SALEM-3T is routines embedded into the software. Ease of calibration is the very easy with the ADSST-SALEM-3T-DK developer’s kit. The key feature in this chipset. By sending specific commands to the kit in the UART mode enables a user to evaluate and test the ADSST-SALEM-3T chipset, the dc offsets and gains for all volt- computational elemen
ページ4に含まれる内容の要旨
ADSST-SALEM-3T This takes place while the processor continues to: GENERAL DESCRIPTION OF THE ADSST-218X DSP The ADSST-218x is a single-chip microcomputer optimized for • Receive and transmit data through the two serial ports digital signal processing (DSP) and other high speed numeric • Receive and/or transmit data through the internal processing applications. DMA port The DSP combines the ADSP-2100 family base architecture • Receive and/or transmit data through the byte DMA port (
ページ5に含まれる内容の要旨
ADSST-SALEM-3T Efficient data transfer is achieved with the use of five internal The ADSST-218x can respond to 11 interrupts. There are up to buses: six external interrupts (one edge sensitive, two level sensitive, and three configurable) and seven internal interrupts generated • Program Memory Address (PMA) Bus Program Memory by the timer, the serial ports (SPORTs), the byte DMA port, and Data (PMD) Bus the power-down circuitry. There is also a master RESET signal. The two serial port
ページ6に含まれる内容の要旨
ADSST-SALEM-3T ADSST-218X COMMON-MODE PINS Table 2. Pin Name No. of Pins I/O Function BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output BMS 1 O Byte Memory Select Output BR 1 I Bus Request Input CMS 1 O Combined Memory Select Output DMS 1 O Data Memory Select Output IOMS 1 O Memory Select Output PMS 1 O Program Memory Select Output RD 1 O Memory Read Enable Output RESET 1 I Processor Reset Input WR 1 O Memory Write Enable Output 1 IRQ2/ 1 I Edge- or Level-Sensitive Interrupt
ページ7に含まれる内容の要旨
ADSST-SALEM-3T CLOCK SIGNALS RESET Either a crystal or a TTL compatible clock signal can clock the The signal initiates a master reset of the ADSST-2185x. RESET ADSST-218x. The RESET signal must be asserted during the power-up sequence to assure proper initialization. during initial RESET If an external clock is used, it should be a TTL compatible signal power-up must be held long enough to enable the internal clock running at half the instruction rate. The signal is connected to
ページ8に含まれる内容の要旨
ADSST-SALEM-3T ADSST-218X ELECTRICAL CHARACTERISTICS Table 4. Parameter Test Conditions Min Typ Max Unit 1, 2 V High Level Input Voltage @ V = Max 1.5 V IH DDINT VIH High Level CLKIN Voltage @ VDDINT = Max 2.0 V 1, 3 VIL Low Level Input Voltage @ VDDINT = Min 0.7 V 1, 4, 5 V High Level Output Voltage @ V = Min, I = –0.5 mA 2.0 V OH DDEXT OH @ V = 3.0 V, I = –0.5 mA 2.4 V DDEXT OH 6 @ VDDEXT = Min, IOH = –100 µA VDDEXT – 0.3 V 1, 4, 5 V Low Level Output Voltage @ V =
ページ9に含まれる内容の要旨
ADSST-SALEM-3T ABSOLUTE MAXIMUM RATINGS—ADSST-218X Table 5. Rating Parameter Min Max Internal Supply Voltage (VDDINT) –0.3 V +3.0 V External Supply Voltage (V ) –0.3 V +4.0 V DDEXT 1 Input Voltage –0.3 V +4.0 V 2 Output Voltage Swing –0.5 V V + 0.5 V DDEXT Operating Temperature Range 0°C 70°C Storage Temperature Range –65°C +150°C 1 Applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, RESET BR PWD A1–A13, PF0–PF7) and input-only pins
ページ10に含まれる内容の要旨
ADSST-SALEM-3T PIN CONFIGURATION—ADSST-218X 75 A4/IAD3 1 D15 PIN 1 74 A5/IAD4 2 D14 IDENTIFIER 3 73 GND D13 A6/IAD5 4 72 D12 71 A7/IAD6 5 GND A8/IAD7 6 70 D11 69 A9/IAD8 7 D10 8 68 A10/IAD9 D9 A11/IAD10 9 67 V DDEXT 10 66 A12/IAD11 GND A13/IAD12 11 65 D8 12 64 D7/IWR GND ADSST-218x 13 63 D6/IRD CLKIN TOP VIEW 14 62 D5/IAL XTAL (Not to Scale) V 61 15 D4/IS DDEXT 16 60 CLKOUT GND V GND 17 59 DDINT D3/IACK V 18 58 DDINT WR 19 57 D2/IAD15 RD 20 56 D1/IAD14 BMS 21 55 D0/IAD13 54 DMS 22 BG P
ページ11に含まれる内容の要旨
ADSST-SALEM-3T GENERAL DESCRIPTION OF THE ADSST-73360LAR The ADSST-73360LAR is particularly suitable for industrial ADC power metering as each channel samples synchronously, ensur- ing that there is no (phase) delay between the conversions. The The ADSST-73360LAR is a 6-channel input analog front end ADSST-73360LAR also features low group delay conversions on processor for general-purpose applications, including industrial all channels. power metering or multichannel analog inputs. It f
ページ12に含まれる内容の要旨
ADSST-SALEM-3T SPECIFICATIONS—ADSST-73360LAR (AVDD = 2.7 V to 3.6 V, DVDD = 2.7 V to 3.6 V, DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz, TA = TMIN to 1 TMAX , unless otherwise noted.) Table 6. Parameter Min Typ Max Unit Test Conditions REFERENCE REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 Ω Absolute Voltage, V 1.08 1.2 1.
ページ13に含まれる内容の要旨
ADSST-SALEM-3T Parameter Min Typ Max Unit Test Conditions FREQUENCY RESPONSE 7 (ADC) Typical Output Frequency (Normalized to fS) 0 0 dB 0.03125 –0.1 dB 0.0625 –0.25 dB 0.125 –0.6 dB 0.1875 –1.4 dB 0.25 –2.8 dB 0.3125 –4.5 dB 0.375 –7.0 dB 0.4375 –9.5 dB > 0.5 < –12.5 dB LOGIC INPUTS VINH, Input High Voltage VDD – 0.8 VDDV VINL, Input Low Voltage 0 0.8 V IIH, Input Current 10 µA C , Input Capacitanc
ページ14に含まれる内容の要旨
ADSST-SALEM-3T ABSOLUTE MAXIMUM RATINGS—ADSST-73360LAR (TA = 25°C unless otherwise noted) Table 8. Parameter Rating AVDD, DVDD to GND –0.3 V to +4.6 V AGND to DGND –0.3 V to +0.3 V Digital I/O Voltage to DGND –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND –0.3 V to AVDD Operating Temperature Range 0°C to +70°C Storage Temperature Range –65°C to +150°C Maximum Junction Temperature 150°C Thermal Impedance θ (SOIC) 75°C/W JA Stresses above those listed under Absolute Maximum
ページ15に含まれる内容の要旨
ADSST-SALEM-3T PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS—ADSST-73360LAR VINP2 1 28 VINN3 VINN2 2 27 VINP3 VINP1 3 26 VINN4 TOP VIEW (Not to Scale) VINN1 4 25 VINP4 REFOUT 5 24 VINN5 REFCAP 6 23 VINP5 AVDD2 7 22 VINN6 AGND2 8 21 VINP6 DGND 9 20 AVDD1 DVDD 10 19 AGND1 RESET 11 18 SE SCLK 12 17 SDI MCLK 13 16 SDIFS SDO 14 15 SDOFS NC = NO CONNECT 03738-0-005 Figure 7. ADSST-73360LAR Pin Configuration—RW-28 PIN FUNCTION DESCRIPTIONS Table 9. Pin No. Mnemonic Function 1 VINP2 Anal
ページ16に含まれる内容の要旨
ADSST-SALEM-3T Pin No. Mnemonic Function 18 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset
ページ17に含まれる内容の要旨
ADSST-SALEM-3T The ADSST-73360LAR has a peak-to-peak input range of V – REF POWER-UP INITIALIZATION AND DATA FROM THE (V × 0.6525) to V + (V × 0.6525); for V = 2.5 V, this is REF REF REF REF ADSST-SALEM-3T 0.856 V to 4.14 V p-p. This limit defines the resistance network The ADSST-SALEM-3T-EV boot loads the code from the on the potential circuits and the burden resistance on the sec- nonvolatile flash memory as shown in the block diagram of ondary side of the CT. Since the ADSST-7336
ページ18に含まれる内容の要旨
ADSST-SALEM-3T ACCURACY OF REFERENCE DESIGN USING THE ADSST-SALEM-3T CHIPSET Overall Accuracy, Power, and Energy Measurement The accuracy figures are measured under typical specified conditions, unless otherwise indicated. Table 10. Test Conditions for Reference Design Using a µ Metal CT of Class 0.5 Accuracy Parameter Nominal Value Nominal Voltage (Phase to Neutral) VN VN = 230 V ± 1% Maximum Voltage (Phase to Neutral) 300 V Nominal Current I = 5 A N Maximum Current I I = 20 A MAX M
ページ19に含まれる内容の要旨
ADSST-SALEM-3T Table 17. Voltage Unbalance Error Current Voltage Min Typ Max Unit I V + 15% V % N N ±0.1 ±0.2 Table 18. Starting Current Min Typ Max Unit 0.07 0.1 % of I N Rev. 0 | Page 19 of 24
ページ20に含まれる内容の要旨
ADSST-SALEM-3T OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 14.00 BSC SQ 0.75 100 76 12° 1 75 0.60 TYP 0.45 PIN 1 SEATING PLANE 12.00 TOP VIEW REF (PINS DOWN) 10° 6° 1.45 0.20 2° 1.40 0.09 VIEW A 1.35 7° 3.5° 25 51 26 50 0° 0.15 SEATING 0.05 0.08 MAX 0.27 PLANE 0.50 BSC COPLANARITY 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969
