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AMD Geode™ SC1200/SC1201
Processor Data Book
March 2006
Publication ID: 32579B
AMD Geode™ SC1200/SC1201 Processor Data Book
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© 2006 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
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Contents 32579B Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . .
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32579B Contents 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.2 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 32579B List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3-2. BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 4-1. WATCHDOG Block
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32579B List of Figures Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers . . . . . . . . . . . . . . . 319 Figure 7-7. Video Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Figure 7-8. Horizontal Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Figure 7-9. Linear Interpolation Calculation . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 32579B Figure 9-45. Enhanced Parallel Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Figure 9-46. ECP Forward Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Figure 9-47. ECP Reverse Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 Figure 9-48. AC97 Reset Timing Diagram . . . . . . . . . . . . . . . . . . .
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32579B List of Figures 8 AMD Geode™ SC1200/SC1201 Processor Data Book
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List of Tables 32579B List of Tables Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC1200/SC1201 Processor Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3-1. Signal Definitions Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number . . . . . . . . . . . . . . . .
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32579B List of Tables Table 5-29. Banks 0 and 1 - Common Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 119 Table 5-31. ACB Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 5-32. ACB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables 32579B Table 6-22. F3: PCI Header Registers for Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 6-23. F3BAR0: Audio Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary . . . . . . . . . . . . . . . . . . 185 Table 6-25. F5BAR0: I/O Control Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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32579B List of Tables Table 9-17. TV DAC (4 Outputs: CVBS, SVY/TVR, SVC/TVB, CVBS/TVG) . . . . . . . . . . . . . . . . . . . . . 384 Table 9-18. ACCESS.bus Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Table 9-19. ACCESS.bus Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Table 9-20. PCI AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Overview 32579B 1.0Overview 1 1.1 General Description The AMD Geode™ SC1200 and SC1201 processors are � The Core Logic module includes: PC/AT functionality, a members of the AMD Geode processor family of fully inte- USB interface, an IDE interface, a PCI bus interface, an grated x86 system chips. The SC1200/SC1201 processor LPC bus interface, Advanced Configuration Power Inter- includes: face (ACPI) version 1.0 compliant power management, and an audio codec interface. � The Geode GX1 processo
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32579B Overview 1.2 Features General Features Video Processor Module ■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc- ■ Video Accelerator: tion set support — Flexible video scaling support of up to 8x (horizon- tally and vertically) ■ Memory controller with 64-bit SDRAM interface — Bilinear interpolation filters (with two taps, and eight ■ 2D graphics accelerator phases) to smooth output video ■ Video/Graphics Mixer: ■ CRT controller with hardware video accelerator — 8-Bit value alpha b
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Overview 32579B — VBI Generation Support: ■ IDE Interface: – Wide Screen Signaling (WSS) — Two IDE channels for up to four external IDE devices – Closed caption — Supports ATA-33 synchronous DMA mode transfers, – Extended Data Services (EDS) up to 33 MB/s – Copy Generation Management System (CGMS) ■ Universal Serial Bus (USB): — Four-field NTSC or eight-field PAL generation — USB OpenHCI 1.0 compliant — Macrovision copy protection version 7.1.L1 (SC1201 — Three ports only, see "Macrovision Pro
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32579B Overview 16 AMD Geode™ SC1200/SC1201 Processor Data Book
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Architecture Overview 32579B 2.0Architecture Overview 2 As illustrated in Figure 1-1 on page 13, the SC1200/ The SC1200/SC1201 processor’s device ID is contained in SC1201 processor contains the following modules in one the GX1 module. Software can detect the revision by read- integrated device: ing the DIR0 and DIR1 Configuration registers (see Config- uration registers in the AMD Geode™ GX1 Processor Data � GX1 Module: Book). The AMD Geode™ SC1200/SC1201 Processor — Combines advanced CPU perfo
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32579B Architecture Overview Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary GX_BASE+ Width Memory Offset (Bits) Type Name/Function Reset Value 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C0040h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2 00000801h 8408h-840Bh 32 R/W MC_BANK_CFG. Memory Controller Bank Configuration 41104110h 840Ch-840Fh 32 R/W MC_SYNC_TIM1. Memory Controller Synchronous Timing 2A733225h Register 1 84
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Architecture Overview 32579B Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued) Bit Description 4 RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin is enabled, processor, graphics pipeline, and low priority display con- troller requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority leve
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32579B Architecture Overview Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued) Bit Description GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 only) 1: 2 Module banks (Bank 0 and 1) 13 RSVD (Reserved). Write as 0. 12 SODIMM_COMP_BNK (SODIMM Com
