ページ1に含まれる内容の要旨
User’s Guide
2005 Mixed Signal Products
SLAU049E
ページ2に含まれる内容の要旨
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the t
ページ3に含まれる内容の要旨
Related Documentation From Texas Instruments Preface About This Manual This manual discusses modules and peripherals of the MSP430x1xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device fa
ページ4に含まれる内容の要旨
Glossary Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www.ti.com/msp430 for application reports CPU Central Processing Unit See RISC 16-Bit CPU DAC Digital-to-Analog Converter DCO Digitally Controlled Oscillator See Basic Clock Module dst Destination See RISC 16-Bit CPU FLL Frequency Locked Loop See FLL+ in MSP430x4xx Family User’s Guide GIE General Interrupt En
ページ5に含まれる内容の要旨
Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 (w) No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. h0 Cleared by hardware h1 Set by hardware −0,−1 Condition after
ページ6に含まれる内容の要旨
vi
ページ7に含まれる内容の要旨
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Embedded Emulation . . . . . .
ページ8に含まれる内容の要旨
Contents 3 RISC 16-Bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.1 Program Counter (PC) . . . . . . . . . . . . .
ページ9に含まれる内容の要旨
Contents 6 Supply Voltage Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 SVS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 SVS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 Configuring the SVS . . . . . . . . . . . . . . . . . .
ページ10に含まれる内容の要旨
Contents 10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.1 Watchdog Timer Counter . . . . . . . . . . . . . . . . . . . . .
ページ11に含まれる内容の要旨
Contents 14 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ12に含まれる内容の要旨
Contents 18 ADC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1 ADC10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 ADC10 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.2.1 10-Bit ADC Core . . . . . . . . . . . . .
ページ13に含まれる内容の要旨
Chapter 1 This chapter describes the architecture of the MSP430. Topic Page 1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . .
ページ14に含まれる内容の要旨
Architecture 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x1xx family include: Ultralow-power architecture extends battery life 0.1-µA RAM retention 0.8-µA real-ti
ページ15に含まれる内容の要旨
Embedded Emulation Figure 1−1. MSP430 Architecture ACLK Clock Flash/ RAM Peripheral Peripheral Peripheral ROM System SMCLK MCLK MAB 16-Bit RISC CPU 16-Bit Bus MDB 16-Bit MDB 8-Bit Conv. JTAG ACLK SMCLK Peripheral Peripheral Peripheral Watchdog Peripheral 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: Unobtrusive development and debug with full-speed
ページ16に含まれる内容の要旨
Address Space 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is 64 KB with future expansion planned. Figure 1−2. Memory Map Access 0FFFFh Word/Byte Interrupt Vector Table 0FFE0h
ページ17に含まれる内容の要旨
Address Space 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules should be accessed with byte instructions. Read access of byte mo
ページ18に含まれる内容の要旨
1-6 Introduction
ページ19に含まれる内容の要旨
Chapter 2 This chapter describes the MSP430x1xx system resets, interrupts, and operating modes. Topic Page 2.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
ページ20に含まれる内容の要旨
System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated. Figure 2−1. Power-On Reset and Power-Up Clear Schematic V V V V CC CC CC CC Brownout POR POR POR S ‡ # # Reset POR Detect Detect Delay S POR Latch R 0 V 0 V 0 V 0 V 0 V ~ 50us Delay § SVS_P
