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10.9MHz–1175MHz Low Phase Noise
Clock Evaluation Board
User's Guide
March 2007 Serial Link Products
SCAU020
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2 SCAU020–March 2007 Submit Documentation Feedback
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Contents 1 General Description..................................................................................................... 5 2 Signal Path and Control Circuitry.................................................................................. 6 3 Block Description........................................................................................................ 7 3.1 Block A ............................................................................................................
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List of Figures 1 CDCE421EVM Evaluation Board.......................................................................................... 5 2 CDCE421EVM Programming Blocks...................................................................................... 6 3 Software Installation Screen................................................................................................ 8 4 Installation Prompt............................................................................................
ページ5に含まれる内容の要旨
User's Guide SCAU020–March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board Figure 1. CDCE421EVM Evaluation Board Features: • Easy-to-use evaluation module generates low phase noise clocks between 10.9MHz—1175MHz • Simple device programming via host-powered USB port • Fast configuration through provided software GUI • Total board power provided either through USB port or separate 3.3V and ground connections • LVCMOS input interface or crystal input • Standard 6-pin XO package connecti
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www.ti.com Signal Path and Control Circuitry 2 Signal Path and Control Circuitry The CDCE421 can accept a 27MHz—38.33MHz frequency input from either an LVCMOS source (up to 3.3V) or a crystal in the same frequency range. The CDCE421EVM is divided into four blocks. The programming section and device power for each sector can be enabled or disabled through individual switches provided for each block. For example, in order to enable power and programming for Block A, the switch must be in the setti
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www.ti.com Block Description 3 Block Description This section discusses the four EVM blocks. 3.1 Block A Block A includes a CDCE421 QFN device that accepts an LVCMOS reference input through the vertical SMA input connector (Ref Input) which is ac-coupled onto the board. 3.2 Block B This block includes a CDCE421 QFN device that uses an AT-cut crystal. This block can be used as either an XO or a VCXO. For use as an XO or VCXO, the crystal should be mounted on either of the two crystal footprints o
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www.ti.com Installing the Software GUI and USB Driver 5 Installing the Software GUI and USB Driver ® The CDCE421EVM software can be installed on a PC running the Microsoft Windows 2000 operating ® system or higher (including Windows XP ). To start software installation, run the ChronosSetup.msi file (available on the CD shipped with the EVM). Figure 3 appears. Be sure to note the installation folder; the USB driver must be installed in the same after setup completes and the USB cable is connecte
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www.ti.com ChronosGUI After the setup wizard completes, start the GUI interface from the Start menu (Start→Texas Instruments→Chronos Eval→TIChronosGUI.exe). Connect the USB cable to the EVM. If Microsoft Windows prompts you for an appropriate driver, do not use the automatic search option. Select a manual installation. When prompted for the driver location, browse to the Chronos GUI file folder that was created during installation. (If the operating system does not ask for a driver, no additiona
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www.ti.com ChronosGUI frequency should be entered here in this format: xx.xxx (specified in MHz). Step 3. Output Calculator and Apply PLL Settings. The second row of calculations is used to obtain the PLL settings necessary to achieve a particular output frequency provided a given input frequency to CDCE421. The input must be entered in the second row as well as the location provided at the input of the PLL block diagram. After the Calculate button is pressed, the adjacent drop-down menu populat
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www.ti.com ChronosGUI 6.2 Manual PLL Block Selection (Advanced Control) The advanced control screen helps to set the PLL without having to manually alter the individual blocks within the PLL. If a user is familiar with PLL operation, one may activate individual control of the PLL blocks by clicking on the Advanced Control button, activating the window shown in Figure 7. Figure 7. Chronos GUI—Manual PLL Block Selection Pop-Up SCAU020–March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Boa
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www.ti.com ChronosGUI Table 1 lists the various menu items in this screen. Table 1. Software Settings Description Section Function VCO Select Selects between VCO1 and VCO2. Only one VCO can be used during operation. See CDCE421 data sheet for VCO tuning ranges. Prescalar The prescalar selection is determined in conjunction with VCO and output divider selection. See the CDCE421 data sheet to determine the proper setting. Output Divider The output divider is determined in conjunction with the VCO
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www.ti.com Configuring the Board 7 Configuring the Board The CDCE421EVM can be powered from the USB power supply or from an external source. The CDCE421EVM only needs a USB cable attached for programming purposes; however, for test measurements it is recommended to also use an external 3.3V power supply. Test measurements can also be taken with only the USB supplied power. Note that because of USB power variance, results may degrade. It is also possible to program the CDCE421 and then disconnect
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www.ti.com Schematics and Layout Figure 9. CDCE421EVM Block Switch Off 8 Schematics and Layout Figure 10 through Figure 14 show the printed circuit board (PCB) schematics. Note: Board layouts are not to scale. These figures are intended to show how the board is laid out; they are not intended to be used for manufacturing CDCE421EVM PCBs. 14 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board SCAU020–March 2007 Submit Documentation Feedback
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www.ti.com Schematics and Layout Figure 10. CDCE421EVM Board Schematic SCAU020–March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 15 Submit Documentation Feedback
ページ16に含まれる内容の要旨
www.ti.com Schematics and Layout Figure 11. CDCE421EVM Board—Block A Schematic 16 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board SCAU020–March 2007 Submit Documentation Feedback
ページ17に含まれる内容の要旨
www.ti.com Schematics and Layout Figure 12. CDCE421EVM Board—Block B Schematic SCAU020–March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 17 Submit Documentation Feedback
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www.ti.com Schematics and Layout Figure 13. CDCE421EVM Board—Block C Schematic 18 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board SCAU020–March 2007 Submit Documentation Feedback
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www.ti.com Schematics and Layout Figure 14. CDCE421EVM Board—Block D Schematic SCAU020–March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 19 Submit Documentation Feedback
ページ20に含まれる内容の要旨
EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be
