ページ1に含まれる内容の要旨
Rev. 1.0, Sep. 2010
M391B5773DH0
M391B5273DH0
240pin Unbuffered DIMM
1.35V
based on 2Gb D-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain
ページ2に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First Release Sep. 2010 - S.H.Kim - 2 -
ページ3に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM Table Of Contents 240pin Unbuffered DIMM based on 2Gb D-die 1. DDR3L Unbuffered DIMM Ordering Information...........................................................................................................4 2. Key Features.................................................................................................................................................................4 3. Address Configuration ....................................
ページ4に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 1. DDR3L Unbuffered DIMM Ordering Information Number of 2 Density Organization Component Composition Height Part Number Rank M391B5773DH0-YF8/H9/K0 2GB 256Mx64 256Mx8(K4B2G0846D-HY##)*9 1 30mm M391B5273DH0-YF8/H9/K0 4GB 512Mx72 256Mx8(K4B2G0846D-HY##)*18 2 30mm NOTE : 1. "##" - F8/H9/K0 2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
ページ5に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 4. x72 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back V V V 1 121 42 NC 162 NC 82 DQ33 202 REFDQ SS SS V V V 2 122 DQ4 43 NC 163 83 203 DM4 SS SS SS 3 DQ0 123 DQ5 44 V 164 CB6 84 DQS4204 NC SS V V 4 DQ1 124 45 CB2 165 CB7 85 DQS4 205 SS SS V V V 5 125 DM0 46 CB3 166 86 206 DQ38 SS SS SS 3 V 6DQS0 126 NC 47 167 NC (TEST) 87 DQ34 207 DQ39 SS V V 7 DQS0 127 48 NC 168 Reset 88 DQ35 208 SS SS 8 V 1
ページ6に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 5. Pin Description Pin Name Description Pin Name Description 2 A0-A14 SDRAM address bus SCL I C serial bus clock for EEPROM 2 BA0-BA2 SDRAM bank select SDA I C serial bus data line for EEPROM 2 RAS SDRAM row address strobe SA0-SA2 I C serial address select for EEPROM CAS SDRAM column address strobe V * SDRAM core power supply DD V * WE SDRAM write enable SDRAM I/O Driver power supply DDQ S0, S1 DIMM Rank Select Lines V SDRAM I/O reference supply RE
ページ7に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 7. Input/Output Functional Description Symbol Type Function CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive CK0-CK1 SSTL edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of CK0-CK1 crossing) Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low CKE0-CKE1
ページ8に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 7.1 Address Mirroring Feature There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces. The pins o
ページ9に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 8. Function Block Diagram: 8.1 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) S0 DQS0 DQS4 DQS0 DQS4 DM0 DM4 DM CS DQS DQS DM CS DQS DQS DQ0 DQ32 I/O 0 I/O 0 DQ1 I/O 1 DQ33 I/O 1 D0 D4 DQ2 DQ34 I/O 2 I/O 2 DQ3 I/O 3 DQ35 I/O 3 DQ4 I/O 4 DQ36 I/O 4 DQ5 DQ37 I/O 5 I/O 5 ZQ ZQ DQ6 I/O 6 DQ38 I/O 6 DQ7 DQ39 I/O 7 I/O 7 DQS1 DQS5 DQS1 DQS5 DM1 DM5 DM CS DQS DQS DM CS DQS DQS DQ8 I/O 0 DQ40 I/O 0 DQ9 DQ41 I/O 1 I/O 1 D1 D5 DQ10 I/O 2 DQ42
ページ10に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 8.2 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) S1 S0 DQS0 DQS4 DQS0 DQS4 DM0 DM4 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ0 I/O 0 I/O 0 DQ32 I/O 0 I/O 0 DQ1 DQ33 I/O 1 I/O 1 I/O 1 I/O 1 D0 D9 D4 D13 DQ2 I/O 2 I/O 2 DQ34 I/O 2 I/O 2 DQ3 I/O 3 I/O 3 DQ35 I/O 3 I/O 3 DQ4 DQ36 I/O 4 I/O 4 I/O 4 I/O 4 DQ5 I/O 5 I/O 5 DQ37 I/O 5 I/O 5 DQ6 DQ38 I/O 6 I/O 6 I/O 6 I/O 6 DQ7 I/O 7 I/O 7 DQ39 I/O 7 I/O 7 ZQ ZQ ZQ ZQ DQS1
ページ11に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 9. Absolute Maximum Ratings 9.1 Absolute Maximum DC Ratings Symbol Parameter Rating Units NOTE V Voltage on V pin relative to V -0.4 V ~ 1.975 V V 1,3 DD DD SS V Voltage on V pin relative to V -0.4 V ~ 1.975 V V 1,3 DDQ DDQ SS V V Voltage on any pin relative to V -0.4 V ~ 1.975 V V 1 IN, OUT SS T Storage Temperature -55 to +100 °C 1, 2 STG NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to th
ページ12に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11. AC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 2 ] Single Ended AC and DC input levels for Command and Address DDR3-800/1066/1333/1600 Symbol Parameter Unit NOTE Min. Max. 1.35V a) V (DC90) V + 90 V DC input logic high mV IH.CA REF DD 1,5 a) V (DC90) V V - 90 DC input logic low mV 1,6 IL.CA SS REF V (AC160) V + 160 AC input logic high Note 2 mV 1,2 IH.CA REF V (AC160) V - 160 AC input logic lo
ページ13に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM [ Table 3 ] Single Ended AC and DC input levels for DQ and DM DDR3-800/1066 DDR3-1333/1600 Symbol Parameter Unit NOTE Min. Max. Min. Max. 1.35V a) V (DC90) V + 90 V V + 90 V DC input logic high mV IH.DQ REF DD REF DD 1,5 a) V (DC90) V V - 90 V V - 90 DC input logic low mV 1,6 IL.DQ SS REF SS REF V (AC160) V + 160 AC input logic high Note 2 - - mV 1,2 IH.DQ REF V (AC160) V - 160 AC input logic low Note 2 -- mV1,2 IL.DQ REF V (AC135) V + 135 V + 135
ページ14に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11.2 V Tolerances REF The dc-tolerance limits and ac-noise limits for the reference voltages V and V are illustrate in Figure 2. It shows a valid reference voltage REFCA REFDQ V (t) as a function of time. (V stands for V and V likewise). REF REF REFCA REFDQ V (DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V . Fur- REF REF REF thermore V (t) may temporarily dev
ページ15に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11.3 AC and DC Logic Input Levels for Differential Signals 11.3.1 Differential Signals Definition tDVAC V .DIFF.AC.MIN IH V .DIFF.MIN IH 0.0 half cycle V .DIFF.MAX IL V .DIFF.AC.MAX IL tDVAC time Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC 11.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) DDR3-800/1066/1333/1600 Symbol Parameter 1.35V 1.5V unit NOTE min max min max V differential input
ページ16に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM [ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V) tDVAC [ps] @ |V (AC)| = 320mV tDVAC [ps] @ |V (AC)| = 270mV IH/Ldiff IH/Ldiff Slew Rate [V/ns] min max min max > 4.0 TBD - TBD - 4.0 TBD - TBD - 3.0 TBD - TBD - 2.0 TBD - TBD - 1.8 TBD - TBD - 1.6 TBD - TBD - 1.4 TBD - TBD - 1.2 TBD - TBD - 1.0 TBD - TBD - < 1.0 TBD - TBD - [ Table 5 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V) tDVAC [ps] @
ページ17に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V min / V max (approximately equal to the ac-levels ( V (AC) / V (AC) ) for ADD/CMD signals) in every SEH SEL IH IL half-cycle. DQS, DQS have to reach V min / V max (approximately the ac-levels ( V (AC) / V (AC) )
ページ18に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V is measured from the actual IX cross point of true and complement signal to the mid level between of V and V . DD SS V DD CK, DQS V
ページ19に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 11.4 Slew Rate Definition for Single Ended Input Signals See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals. 11.5 Slew rate definition for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below. [ Table
ページ20に含まれる内容の要旨
Rev. 1.0 Unbuffered DIMM datasheet DDR3L SDRAM 12.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) and V (AC) OL OH for single ended signals as shown in below. [ Table 12 ] Single ended Output slew rate definition Measured Description Defined by From To V (AC)-V (AC) OH OL V (AC) V (AC) Single ended output slew rate for rising edge OL OH Delta TRse V (AC)-V (AC) OH OL Single ende
