ページ1に含まれる内容の要旨
E‐14
Hardware Technical Reference
Release: 14.1.8.12
Hardware Version: F
Pico E14 Hardware Reference www.picocomputing.com Pico Computing, Inc.
(206) 283‐2178 150 Nickerson Street. Suite 311
Seattle, WA 98109
ページ2に含まれる内容の要旨
2 Contents: Product Overview 4 Quick Reference Datasheet 5 Electrical Specifications 6 System Architecture 7 Features Field Programmable Gate Array 8 Power‐PC™ Processor 9 CPLD TurboLoader 10 Tri‐Mode Ethernet Interface 11 Flash Memory 12 DDR2 Memory 13 I/O Interfaces Analog Interface 14 RS‐232 Serial Interface 15 Digital Peripheral Interface 16 CardBus Interface 17 Digital Bus Interface 18 JTAG Debug Interface 19 Appendices A
ページ3に含まれる内容の要旨
3 Product Overview: The Pico families of product are revolutionary embedded platforms. With performance that often exceeds modern microcomputers, a shockingly small form factor, and nominal power consumption that is less than one watt, the Pico family of products takes computing to a whole new level. The Pico E‐14 is based on the revolutionary Virtex‐4 chip. This device has the performance and power consumption of a custom chip (ASIC), but is completely reconfigurable! The Pico E‐14
ページ4に含まれる内容の要旨
4 Pico E-14 EP Quick Reference Datasheet Core Technologies Features - Virtex-4 FPGA - Complete Cardbus host interface capable of bus - PowerPC-405 450 MHz (680 DMIPS) speeds up to 1 Gbps - 256 MB RAM - DSP capability of the Virtex-4 FPGA - 64 MB FPGA Image Flash - Bus interface re-configurable to fit other bus nterface - Analog to Digital and Digital to Analog protocols Converters - Works with Xilinx standard tool set (ISE, EDK, and - Gigabit Ethernet (1000/100/10 Mbps) Platform SDK)
ページ5に含まれる内容の要旨
5 Pico E‐14 Electrical Specifications Minimum Nominal Maximum DC Input Voltage 3.15V 3.3‐5.0V 5.5V Power Consumption 10W* Recommended Temperature Range 0°C 10°C 70°C Maximum Allowable Temperature Range 0°C 85°C Continuous Storage Temperature Range ‐50°C 30°C 125°C Relative Humidity (Non‐Condensing) 0% 95% Note: If the card draws more than 10 watts the power supplies cut off and reset the card Power Consumption The graph below has power consumption run
ページ6に含まれる内容の要旨
6 System Architecture At the core of the Pico E‐14 is a Virtex‐4 FPGA. The FPGA can be dynamically configured to perform any number of specialized tasks such as: protocol processing, encryption, or complex mathematical functions. Embedded systems benefit from the integrated Power‐PC™ processor available on the EP series cards. Gigabit Ethernet Analog Converters Serial Transceiver I/O JTAG DSP RAM Slices GPIO DDR2 RAM Flash ROM Figure 1 E‐14 Hardware Reference Manual ww
ページ7に含まれる内容の要旨
7 Field Programmable Gate Array The core of the Pico E‐14 is a high performance Virtex‐4 FPGA. Included in the FPGA are the FPGA Fabric, a Power‐PC ™ processor, ultra high‐speed DSP slices and DDR2 RAM. FPGA Fabric: The “Fabric” of an FPGA comprises an array of logic elements that can be connected in virtually unlimited patterns. These patterns of logic elements can be used to perform basic mathematical functions such as addition and subtraction, or can be grouped together to perf
ページ8に含まれる内容の要旨
8 PowerPC™ Processor PPC405x3 Processor Introduction: FPGAs are renowned for their ability to process parallel logic, but they typically have a hard time emulating a high performance processor. To get the best of both worlds the Virtex‐4™ features an embedded Power PC Processor. Since the processor shares the same die as the FPGA it seamlessly interfaces with the FPGA fabric. A new feature of the Vitex‐4 FPGA is the addition of an auxiliary processor interface. The APU is the hig
ページ9に含まれる内容の要旨
9 CPLD TurboLoader A CPLD (Complex Programmable Logic Device) is a smaller version of an FPGA (described above) with permanent Flash storage built in. The Pico E‐14 contains one CPLD that loads and reconfigures the FPGA. The Pico firmware guide describes how to access the CPLD Image Manager. CPLD Resources: Xilinx CPLD Website www.xilinx.com/cpld E‐14 Hardware Reference Manual www.picocomputing.com Pico Computing, Inc.
ページ10に含まれる内容の要旨
10 Tri‐Mode Ethernet Interface The Pico E‐14 features the Marvell Alaska series 88E1111 tri‐mode Ethernet transceiver. On EP series parts the MAC (Middle access controller) is implemented on the FPGA die. On LO series parts the MAC must be implemented in firmware. Communication between the MAC and PHY takes place over an industry standard MII/GMII interface. The Ethernet transceiver features 10/100/1000 full/half duplex operation. It will automatically configure the physical interf
ページ11に含まれる内容の要旨
11 Flash Memory The Pico E‐14 comes equipped with at least 64 megabytes of Flash ROM. The Flash ROM is divided into 512 sectors that can be erased independently. Most of the space on the ROM is reserved for the user. The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA, but not both. During power‐up or reboot, the TurboLoader is in control of the Flash ROM Address bus. At all other times the FPGA is in control of the address bus. Fi
ページ12に含まれる内容の要旨
12 DDR2 Memory The Pico E‐14 comes equipped with 256 MB of PC‐266 DDR2 memory. There are four 256Mb chips each with 16 bit data paths that are grouped into two 32 bit banks. From 0°C to +95°C, the ram can run at 266 MHz. For operation at temperatures below 0°C, special firmware with reduced ram timings is required. The temperature compensated self‐refresh mode must be disabled below ‐20°C. 16x16 16x16 Bank 1 (LSBs) (MSBs) FPGA 16x16 16x16 Bank 2 (LSBs) (MSBs) Figure 3 E‐1
ページ13に含まれる内容の要旨
13 Analog Interface (Optional) The Pico E‐14 also comes equipped with two high‐speed analog converters each capable of 14‐bit resolution. By default, both analog converters are powered down until the sleep lines are driven low and the amplifier lines are driven high by the FPGA. Both converters are capacitively coupled with pull‐ down resistors on the output to filter out any DC signal components. Both amplifiers are configured for minimum noise and unity gain. 8‐Bit, 80 MSPS Ana
ページ14に含まれる内容の要旨
14 *Please refer to the Analog Interface Selection Guide in Appendix E for compatible 8‐12‐bit converters RS‐232 Serial Transceiver The Pico E‐14 contains one asynchronous RS‐232 serial transceiver that also meets EIA/TIA‐232 and V.28/V.24 specifications at a maximum data rate of 250kBps. Because the serial transceiver is directly connected to the FPGA any bit high‐level protocol can be implemented in logic. Pico Computing supports various asynchronous, synchronous and military serial
ページ15に含まれる内容の要旨
15 Digital Peripheral Interface The Pico E‐14 features 16 GPIO lines that are used for external peripheral support. Pulling the DIAG_EN pin low replaces 4 GPIO signals with JTAG signals. All GPIO signals have user selectable pull‐up, pull‐down, keeper or HI‐Z termination. Drive strength is also user selectable between 2 and 24mA. All GPIOs can be configured for input, output and bi‐ directional mode and are equipped with ESD protection. DIAG_EN State JTAG GPIO Float / High Disab
ページ16に含まれる内容の要旨
16 CardBus Interface The Pico E‐14 can run as a standalone product or be connected to a host using the CardBus connector. By default, the Pico E‐14 ships with firmware that is ready for use as a CardBus slave device, but it also 1 supports bus mastering. That same firmware also provides the means to switch into standlone mode. CardBus is a 32‐bit interface with a maximum speed of 33 MHz. The Pico E‐14 hardware is designed to support standard PCMCIA as well as DMA mode. The CardBus s
ページ17に含まれる内容の要旨
17 Digital Bus Interface When the Pico E‐14 is not connected to a CardBus host, the digital bus can be reconfigured to connect with a wide variety of high‐speed digital busses and peripherals. All signals have user selectable pull‐ up, pull‐down, keeper or HI‐Z termination. Drive strength is also user selectable between 2 and 24mA. All pins can be configured for input, output and bi‐directional mode. With proper termination, speeds of over 200 MHz are possible. The external digital bu
ページ18に含まれる内容の要旨
18 JTAG Debug Interface The Pico E‐14 is equipped with a JTAG diagnostic port that allows real‐time debugging of hardware, firmware and software. Use of the external JTAG port disables four external GPIO pins as well as the internal JTAG loop back. Some JTAG programs require the length of the instruction register (IR). The IR length is listed below for all devices in the JTAG chain. Device Instruction register bit length FX20 FX60 FPGA 10 14 TurboLoader 8 Ethernet PHY
ページ19に含まれる内容の要旨
19 Appendix A – Peripheral I/O Connector Information Connector Information Description Brand Part Number Mating Connector Hirose NX30TA‐32PAA(50) Mating Connector Backshell Hirose NX‐32TA‐CV1(50) *Connectors are always in stock at Pico Computing Peripheral I/O Connector Pinout 1 ETHER_OUT_DD‐ Ethernet (Magnetically Isolated) 2 ETHER_OUT_DD+ Ethernet (Magnetically Isolated) 3 GPIO_15_FILTERED General purpose I/O 4 GPIO_14_FILTERED General purpose I/O 5 GPIO_13_FIL
ページ20に含まれる内容の要旨
20 Peripheral Connector Pin #1 Location Figure 5 Appendix B – CardBus Connector Information Connector Information Description Brand Part Number CardBus Header Hirose IC9‐68RD‐0.635SF‐(51) The Pico E‐14 will mate with any Type‐II CardBus Header The function and direction of the pins on the CardBus interface can be easily changed. Please see the “Digital Bus Interface” section for more information. CardBus Connector Pinout Name Pin Description Dir GND 1 Card Ground
