ページ1に含まれる内容の要旨
P Pi ic co o C Co om mp pu ut ti in ng g
P Pi ic co o C Co om mp pu ut ti in ng g
Pico E-15
Hardware Technical
Reference
Release: 1.01
For Hardware Revision: D
www.picocomputing.com Pico Computing
(206) 283-2178 150 Nickerson Street. Suite 311
Seattle, WA 98109
ページ2に含まれる内容の要旨
2 Contents: Product Overview 3 Quick Reference Datasheet 4 Standard Part Numbers 5 System Architecture 6 Electrical Specification 7 Features Field Programmable Gate Array 8 PowerPC™ Processor 9 CPLD TurboLoader 10 Flash Memory 11 DDR2 SDRAM Memory 12 Temperature Sensor 14 I/O Interfaces Sleep Controller 15 Tri-Mode Ethernet Interface 16 Digital Peripheral Interface 17 High Speed Analog to Digital
ページ3に含まれる内容の要旨
3 Product Overview: The Pico family of products are revolutionary FPGA based embedded acceleration platforms. With performance that often exceeds modern microcomputers, a shockingly small form factor, and nominal power consumption that is less than one watt, the Pico family of products take computing to a whole new level. The Pico E-15 is based on the high-performance Virtex-4 FPGA chip. This device has the performance and power consumption of a custom chip (ASIC), but is completely
ページ4に含まれる内容の要旨
4 Pico E-15 Quick Reference Datasheet FEATURES MECHANICAL Temperature Range: 0°C to +70°C ♦ High-performance Virtex-4 FX-20, 40 or 60 PC Card Type II Form-Factor ♦ 256MB RAM Stainless steel case ♦ 64MB Flash ROM ♦ Dual 12-Bit 125 MSPS A/D converters ♦ Dual 14-Bit 210 MSPS D/A converters POWER ♦ Integrated composite video capture Sleep: 0.001W ♦ CardBus (PCI) Interface Nominal: 1.2W ♦ Open source Absolute Maximum: 7.0W ♦ Standalone operation Supply Voltage: 3.3V ♦
ページ5に含まれる内容の要旨
5 Standard Part Numbers Standard Part Number FX-20 E15FX20-256/64/JEGSAADDV10C FX-40 E15FX40-256/64/JEGSAADDV10C FX-60 E15FX60-256/64/JEGSAADDV10C A Military version is available which includes: BGA underfill Conformal coating Extended temperature range The Military version is available by special order only, and is subject to minimum quantity requirements. Pico E-15 Hardware Reference www.picocomputing.com Pico Computing (206) 283-2178 150 Nickerson
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6 System Architecture At the core of the Pico E-15 is a Virtex-4 FPGA. The FPGA can be dynamically configured to perform any number of specialized tasks such as: protocol processing, encryption, or complex mathematical functions. Embedded systems benefit from the integrated PowerPC™ processor. Pico E-15 Hardware Reference www.picocomputing.com Pico Computing (206) 283-2178 150 Nickerson Street. Suite 311 Seattle, WA 98109
ページ7に含まれる内容の要旨
7 Pico E-15 Electrical Specification Minimum Nominal Maximum DC Input Voltage 3.25V 3.3V 3.35V Power Consumption 0.001W 1.2W 7.0W DC Input Current 0.0003A 0.36A 2.1A Recommended Temperature Range 0°C 10°C 70°C FPGA Over Temperature Shutdown 70-80°C Maximum Storage Temperature Range -50°C 27°C 90°C Relative Humidity (Non-Condensing) 0% 95% Overpower Considerations: The Pico E-15 FX60 is designed desktop computers, and is not recommended for use in laptops. B
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8 Field Programmable Gate Array The core of the Pico E-15 is a high performance Virtex-4 FPGA. Included in the FPGA are the FPGA Fabric, an optional PowerPC ™ processor, ultra high-speed DSP slices and RAM. FPGA Fabric: The “Fabric” of an FPGA comprises an array of logic elements that can be connected in virtually unlimited patterns. These patterns of logic elements can be used to perform basic mathematical functions such as addition and subtraction, or can be grouped togeth
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9 PowerPC™ Processor PPC405x3 Processor Introduction: FPGAs are renowned for their ability to process parallel logic, but they typically have a hard time emulating a high performance processor. To get the best of both worlds the Virtex-4™ features an embedded Power PC Processor. Since the processor shares the same die as the FPGA it seamlessly interfaces with the FPGA fabric. A new feature of the Virtex-4 FPGA is the addition of an auxiliary processor interface. The APU is the
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10 CPLD TurboLoader A CPLD (Complex Programmable Logic Device) is a smaller version of an FPGA (described above) with permanent Flash storage built in. The Pico E-15 contains one CPLD that loads and reconfigures the FPGA. The Pico firmware guide describes how to access the CPLD TurboLoader. The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address bus.
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11 Flash Memory The Pico E-15 comes equipped with at least 64MB of Flash ROM. The Flash ROM is divided into 512 sectors that can be erased independently. Most of the space on the ROM is reserved for the user. The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address bus. At all other times the FPGA is in control of the address bus. The Flash ROM has a si
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12 DDR2 SDRAM Memory The Pico E-15 comes equipped with 256MB of DDR2 SDRAM memory. There are two 1024Mb chips, each with a separate 16 bit data path to the host to form one 32 bit bank. From 0°C to +85°C, the ram can run at up to 333 MHz. For operation at temperatures below 0°C, special firmware with throttled ram timings is required. Please note that the RAM will not function below 125 MHz. RAM MSBs Virtex-4 FPGA RAM LSBs Pico E-15 Hardware Reference www.picocomputing.
ページ13に含まれる内容の要旨
13 RAM Timing and Parameter Information Parameter Value EDK Value EDK Value 133 MHz 333 MHz Registered No 0 0 Clock Pairs 1 1 1 Memory Banks 1 1 1 IDELAY Controllers 2 2 2 Differential DQs Yes 1 1 Open Row Management No 0 0 On Die Termination Disabled 0 0 ECC Support No 0 0 TMRD 2 Clocks 15000 6000 TWR 15 nS 15000 1500 TWTR 7.5 nS 1 3 TRAS 45 nS 45000 45000 TRC 60 nS 60000 60000 TRFC 127.5 nS 12750 12750 TRCD 15 nS 15000 15000 TRRD 10 nS 10000 10000 TRP 15 nS 15000 15000
ページ14に含まれる内容の要旨
14 Temperature Sensor The Pico E-15 contains one temperature sensor that directly senses the die temperature of the Virex-4 FPGA. The digital interface of the remote temperature sensing chip is connected to the Cypress PSoC. If an overtemperature condition occurs, the PSoC will shutdown the FPGA until the temperature has dropped sufficiently below the shutdown threshold. The setpoints of the temperature shutdown circuit can be reprogrammed via the PSoC debug cable. Electri
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15 Sleep Controller The Pico E-15 contains one Cypress PSoC which is used to generate a clock for the bootloader and control the power state. The E-15 can be placed in a state where it draws almost no power, then wakes up automatically after a set amount of time. The sleep controller can be activated by the FPGA, or the external peripheral interface connector. The protocol for entering sleep state is simple. Simply pulse FPGA_POWERCTL_C for as many seconds as your wish to
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16 Tri-Mode Ethernet Interface The Pico E-15 features the Marvell Alaska series 88E1111 tri-mode Ethernet transceiver. Combined with the on-FPGA MAC (Middle access controller) a complete Ethernet solution is offered. Communication between the MAC and PHY takes place over an industry standard MII/GMII interface. The Ethernet transceiver features 10/100/1000 full/half duplex operation. It will automatically configure the physical interface on the fly for crossover or straight thr
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17 Digital Peripheral Interface The Pico E-15 features 2 GPIO lines which are used for external peripheral support. The GPIO lines are always enabled. All GPIO signals have user selectable pull-up, pull-down, keeper or HI-Z termination. Drive strength is also user selectable between 2 and 24mA. All GPIOs can be configured for input, output and bi-directional mode. GPIO 1 has a 50 ohm resistor in series with the output to allow connectivity with low voltage devices which may
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18 High Speed Analog to Digital Converters The Pico E-15 features 2 high speed analog to digital converters. The converters are optimized for high-frequency, high-performance, low-power, low-noise operation. The converters have integrated DC blocking capacitors, and thus, cannot be used on very low frequency signals. The ADC should be driven by a source with an impedance of 50 ohms. To ensure accuracy at high speeds, the low-jitter 125 MHz reference clock must be used. The conv
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19 Electrical Specifications Minimum Nominal Maximum Differential AC Input Voltage 0 Vpp 1 Vpp 1.8 Vpp Termination Resistance 45 (VHF) 50 (AC) 115(DC) Input Frequency Range 1 KHz* 1-50 MHz 125 MHz Bandwidth 125 MHz 225 MHz Dielectric Surge Withstand Voltage -14 VDC 0 VDC 14 VDC Withstand Voltage -4 VDC 0 VDC 4 VDC Clock Frequency 125 MHz 125 MHz Resolution 12 Bits Sensativity 0.087V 0.013V 0.007V *Lower frequencies are possible with degraded performance. ADC Fro
ページ20に含まれる内容の要旨
20 ADC Low Frequency Input Impedance ADC High Frequency Input Impedance* *Low pass filter range is customizable via special order Pico E-15 Hardware Reference www.picocomputing.com Pico Computing (206) 283-2178 150 Nickerson Street. Suite 311 Seattle, WA 98109
