ページ1に含まれる内容の要旨
User’s Guide
Shop online at
www.omega.com
e-mail: info@omega.com
OME-A822PG
ISA-Bus Multi-Functional Board
Hardware Manual
ページ2に含まれる内容の要旨
® OMEGAnet Online Service Internet e-mail www.omega.com info@omega.com Servicing North America: USA: One Omega Drive, P.O. Box 4047 ISO 9001 Certified Stamford CT 06907-0047 TEL: (203) 359-1660 FAX: (203) 359-7700 e-mail: info@omega.com Canada: 976 Bergar Laval (Quebec) H7L 5A1, Canada TEL: (514) 856-6928 FAX: (514) 856-6886 e-mail: info@omega.ca For immediate technical or application assistance: ® USA and Canada: Sales Service: 1-800-826-6342 / 1-800-TC-OMEGA ® Customer Service: 1-800-622-2378
ページ3に含まれる内容の要旨
OME-A-822PGH/PGL Enhanced Multi-Function Card Hardware Manual OME-A-822PGL/PGH Hardware Manual ---- 1
ページ4に含まれる内容の要旨
Tables of Contents 1. Introduction_________________________________________________________4 1.1 General Description __________________________________________________ 4 1.2 Features _____________________________________________________________ 4 1.3 Specifications _________________________________________________________ 5 1.3.1 Power Consumption :________________________________________________________5 1.3.2 Analog Inputs__________________________________________________
ページ5に含まれる内容の要旨
2.4.9 A/D Software Trigger Control Register _________________________________________ 23 2.4.10 D/O Output Latch Register __________________________________________________ 24 2.5 Digital I/O __________________________________________________________ 25 2.6 8254 Timer/Counter __________________________________________________ 26 2.7 A/D Conversion ______________________________________________________ 27 2.7.1 A/D conversion flow____________________________________________________
ページ6に含まれる内容の要旨
1. Introduction 1.1 General Description The OME-A-822PGL/PGH is a high performance, multifunction analog, digital I/O board for PC AT compatible computers. The OME-A-822PGL provides low gain (0.5,1, 2, 4, 8). The OME-A-822PGH provides high gain (0.5,1,5,10,50,100,500,1000). The OME-A-822PGL/PGH contains a 12-bit ADC with up to 16 single-ended or 8 differential analog inputs. The maximum sample rate of the A/D converter is 100Ksample/sec. There are two 12-bit DACs with voltage outp
ページ7に含まれる内容の要旨
1.3 Specifications 1.3.1 Power Consumption : +5V @960 mA maximum, OME-A-822PGL/PGH Operating temperature : -20 °C to 60 °C 1.3.2 Analog Inputs Channels : 16 single-ended or 8 differential Input range : (software programmable) OME-A-822PGL:bipolar : ±10V, ±5V, ±2.5V, ±1.25V, ±0.0625V unipolar : 0 to 10V, 0 to 5V, 0 to 0.2.5V, 0 to 1.25.V OME-A-822PGH:bipolar : ±10,±5V, ±1V, ±0.5V, ±0.1V, ±0.05V, ±0.01V, ± 0.005V unipolar : 0 to 10V, 0 to 1V, 0 to 0.1V, 0 t
ページ8に含まれる内容の要旨
1.3.4 DA Converter Channels : 2 independent type : 12 bit multiplying , Analog device AD-7541 Linearity : +/- 1/2 bit Output range : 0 to 5V or 0 to 10V jumper selected , may be used with other AC or DC reference input. Maximum output limit +/- 10V Output drive : +/- 5mA settling time : 0.6 microseconds to 0.01% for full scale step 1.3.5 Digital I/O Output port : 16 bits, TTL compatible Output Low: VOL=05.Vmax @IOL = 8 mA max Output High: VOH = 2.7Vmin @IOH =
ページ9に含まれる内容の要旨
1.3.7 Programmable Timer/Counter Type : 82C54 -8 programmable timer/counter Counters : Counter1 and counter2 are cascaded as a 32 bit pacer timer. Counter0 is a user available timer/counter. The software driver also uses counter0 to implement a machine independent timer. Clock input frequency : DC to 10 MHz Pacer output : 0.00047Hz to 0.5MHz Input ,gate : TTL compatible Internal Clock : 2 MHz 1.3.8 Direct Memory Access Channel (DMA) Level : CH1 or CH3, jumper selecta
ページ10に含まれる内容の要旨
1.4 Applications Signal analysis FFT & frequency analysis Transient analysis Production testing Process control Vibration analysis Energy management Industrial and laboratory. measurement and control 1.5 Product Check List The OME-A-8322PGL/PGH includes the following items: OME-A-822PGL/PGH multifunction card OME-A-822PGL/PGH CD ROM Attention ! If any of these items are missing or damaged, please contact our customer service department. Save the shipping
ページ11に含まれる内容の要旨
OME-A-822PGL/PGH VR1/2/3/4/5/6/7 JP2 JP1 CN1 JP3 JP4 CN3 CN2 JP6 SW1 JP7 JP8 JP5 ISA BUS ISA BUS 2. Hardware Configuration 2.1 Board Layout OME-A-822PGL/PGH Hardware Manual ---- 9
ページ12に含まれる内容の要旨
2.2 I/O Base Address Setting The OME-A-822PGL/PGH occupies 16 consecutive locations in I/O address space. The base address is set by DIP switch SW1. The default address is 0x220. A9 A8 A7 A6 A5 A4 ON 1 2 3 4 5 6 SW1 : BASE ADDRESS BASE A9 A8 A7 A6 A5 A4 ADDR 200-20F OFF ON ON ON ON ON 210-21F OFF ON ON ON ON OFF 220-22F( ) OFF ON ON ON OFF ON 230-23F OFF ON ON ON OFF
ページ13に含まれる内容の要旨
The PC I/O port map is given below. ADDRESS Device ADDRESS DEVICE 000-1FF PC reserved 320-32F XT Hard Disk 200-20F Game/control 378-37F Parallel Printer 210-21F XT Expansion Unit 380-38F SDLC 238-23F Bus Mouse/Alt. Bus Mouse 3A0-3AF SDLC 278-27F Parallel Printer 3B0-3BF MDA/Parallel Printer 2B0-2DF EGA 3C0-3CF EGA 2E0-2E7 AT GPIB 3D0-3DF CGA 2E8-2EF Serial Port 3E8-3EF Serial Port 2F8-2FF Serial Port 3F0-3F7 Floppy Disk 300-31F Prototype Card 3F8-3FF Serial Port 2.3 Jumper
ページ14に含まれる内容の要旨
2.3.2 JP2 : D/A Int/Ext Ref Voltage Selection JP2(vref) JP2(vref) Ch 1 = INT Ch 1 =EXT Ch 2 = INT (ExtRef1) (default) Ch 2 =EXT (ExtRef2) JP2(vref) JP2(vref) Ch 1 = INT Ch 1 =EXT Ch 2 =EXT (ExtRef1) (ExtRef2) Ch 2 = INT If JP2 is set to internal reference, then JP1 should be set to -5V or -10V internal reference voltage. If JP2 is set to external reference, then ExtRef1, CN3 pin 31, is the external reference voltage for D/A channel 1. and ExtRef2, CN3 pi
ページ15に含まれる内容の要旨
2.3.4 JP4 : A/D Trigger Source Selection INTTRG Internal External INTTRG Trigger Trigger (default) EXTTRG EXTTRG The OME-A-822PGL/PGH supports two trigger types, internal trigger and external trigger. The external trigger comes from ExtTrg, CN3 pin 17. There are two types of internal triggers, software trigger and pacer trigger. More detailed information is given in section 2.4.8. 2.3.5 JP5 : Interrupt Level Selection NO Interrupt IRQ 3 4 5
ページ16に含まれる内容の要旨
2.3.6 JP6 : User Timer/Counter Clock Input Selection INTCLK Internal 2M External INTCLK Clock Clock (default) EXTCLK EXTCLK The OME-A-822PGL/PGH has 3 independent 16 bit timer/counters. The cascaded counter1 and counter2 are used as a pacer timer. Counter0 can be used as a user programmable timer/counter. The user programmable timer/counter can be set to 2M internal clock or external clock ExtCLK, CN3 pin 37. The block diagram is given in section 2.6. The clock source
ページ17に含まれる内容の要旨
2.3.7 JP7 : DMA DACK Selection, JP8 : DMA DRQ Selection DRQ NO DMA DACK 1 2 1 2 5 6 5 6 JP7 JP8 DRQ DMA 1 DACK 1 2 (default) 1 2 5 6 5 6 JP7 JP8 DRQ DMA 3 DACK 1 2 1 2 5 6 5 6 JP7 JP8 The DMA channel can not shared. The OME-A-822 software driver can support 8 different boards in one PC based system, but only two of these boards can use the DMA transfer function. OME-A-822PGL/PGH Hardware Manual
ページ18に含まれる内容の要旨
2.4 I/O Register Address The OME-A-822PGL/PGH occupies 16 consecutive PC I/O addresses. The following table lists the registers and their locations. Address Read Write Base+0 8254 Counter 0 8254 Counter 0 Base+1 8254 Counter 1 8254 Counter 1 Base+2 8254 Counter 2 8254 Counter 2 Base+3 Reserved 8254 Counter Control Base+4 A/D Low Byte D/A Channel 0 Low Byte Base+5 A/D High Byte D/A Channel 0 High Byte Base+6 DI Low Byte D/A Channel 1 Low Byte Base+7 DI High Byte D/A Channel 1 Hig
ページ19に含まれる内容の要旨
2.4.1 8254 Counter The 8254 Programmable timer/counter has 4 registers from Base+0 through Base+3. For detailed programming information on the 8254 , please refer to Intel‘s “Microsystem Components Handbook”. Address Read Write Base+0 8254 Counter 0 8254 Counter 0 Base+1 8254 Counter 1 8254 Counter 1 Base+2 8254 Counter 2 8254 Counter 2 Base+3 Reserved 8254 Counter Control 2.4.2 A/D Input Buffer Register (READ) Base+4 : A/D Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit
ページ20に含まれる内容の要旨
2.4.3 D/A Output Latch Register (WRITE) Base+4 : Channel 1 D/A Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+5 :Channel 1 D/A High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X D11 D10 D9 D8 (WRITE) Base+6 : Channel 2 D/A Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+7 :Channel 2 D/A High Byte Data Format Bit 7 Bit 6 Bit 5 Bit
