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DSTni-EX User Guide
Section Five
Part Number 900-335
Revision A 3/04
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Copyright & Trademark © 2003 Lantronix, Inc. All rights reserved. Lantronix and the Lantronix logo, and combinations thereof are registered trademarks of Lantronix, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. All other product names, company names, logos or other designations mentioned herein are trademarks of their respective owners. Am186 is a trademark of Advanced Micro Devices, Inc. Ethernet is a registered t
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Warranty Lantronix warrants each Lantronix product to be free from defects in material and workmanship for a period specified on the product warranty registration card after the date of shipment. During this period, if a customer is unable to resolve a product problem with Lantronix Technical Support, a Return Material Authorization (RMA) will be issued. Following receipt of an RMA number, the customer shall return the product to Lantronix, freight prepaid. Upon verification of warranty,
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Contents Copyright & Trademark ________________________________________________________i Warranty___________________________________________________________________ ii Contents___________________________________________________________________ iii List of Tables _______________________________________________________________iv List of Figures_______________________________________________________________vi 1: About This User Guide _________________________________________ 1 Intended Au
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Host Mode Operation________________________________________________________ 50 Sample Host Mode Operations ________________________________________________ 51 USB Pull-up/Pull-down Resistors_______________________________________________ 53 USB Interface Signals _______________________________________________________ 54 5: CAN Controllers _____________________________________________ 55 CANBUS Background _______________________________________________________ 56 Data Exchanges and Commun
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Table 3-17. Clock Control Register ........................................................................................... 28 Table 3-18. Clock Control Register Definitions.......................................................................... 28 Table 3-19. Extended Slave Address Register ......................................................................... 29 Table 3-20. Extended Slave Address Register Definitions........................................................ 29 Tab
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Table 5-34. Tx/Rx Message Level Register .............................................................................. 71 Table 5-35. Tx/Rx Message Level Register Definitions............................................................. 71 Table 5-36. Interrupt Flags........................................................................................................ 72 Table 5-37. Interrupt Flag Definitions..................................................................................
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1: About This User Guide 1: About This User Guide This User Guide describes the technical features and programming interfaces of the Lantronix DSTni-EX chip (hereafter referred to as “DSTni”). DSTni is an Application Specific Integrated Circuit (ASIC)-based single-chip solution (SCS) that integrates the leading-edge functionalities needed to develop low-cost, high-performance device server products. On a single chip, the DSTni integrates an x186 microprocessor, 16K-byte ROM, 256K-byte
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Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic operating principles of microprocessors and their systems and are considering designing systems that utilize DSTni. Conventions This User Guide uses the following conventions to alert you to information of special interest. The symbols # and n are used throughout this Guide to denote active LOW signals. Notes: Notes are information requiring att
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Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is organized into the following chapters and appendixes. Section 1: Introduction Describes the DSTni architecture, design benefits, theory of operations, ball assignments, packaging, and electrical specifications. This chapter includes a DSTni block diagram. Section 2: Microprocessor Describes the DSTni microprocessor and its control registers.
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2: SPI Controller 2: SPI Controller This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include: Theory of Operation on page 4 SPI Controller Register Summary on page 5 SPI Controller Register Definitions on page 6 Theory of Operation SPI Background SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit-tr
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When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is fully synchronous to the CLK signal. As a result, SCLK is sampled and then operated on. This results in a delay of 3 to 4 clocks, which may violate the SPI specification if SCLK is faster than 1/8th of the CPU clock. In master mode, the SPI operates exactly on the proper edges, since the SPI controller is generating SCLK. The SPI controller uses a
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SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. Table 2-2. SPI_DATA Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B800 FIELD /// DATA[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW RW W Table 2-3. SPI_DATA Register Definitions Bits Field Name Description 15:8 /// Reserved Always returns zero. 7:0 DATA[7:0] Data The location where the CPU reads data from or writes data
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CTL Register CTL is the SPI Controller Control register. Table 2-4. CTL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B802 FIELD /// RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW W Table 2-5. CTL Register Definitions Bits Field Name Description 15:8 /// Reserved Always returns zero. 7 IRQENB Interrupt Request Enable 1 = enable the SPI to generate interrupts. 0 = disable the SPI from generating interrupts (default). Auto
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SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. Table 2-6. SPI_STAT Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B804 FIELD /// /// RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R Table 2-7. SPI_STAT Register Definitions Bits Field Name Description 15:8 /// Reserved Always returns zero. 7 IRQ Interrupt Request 1 = indicates the end of a master mode transfer, or that SLVSEL_N input has gone H
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SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. Table 2-8. SPI_SSEL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B806 FIELD /// BCNT[2:0] /// RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-9. SPI_SSEL Register Definitions Bits Field Name Description 15:8 /// Reserved Always returns zero. 7:6 BCNT[2:0] Bit Shift Count Controls the number of bits shifted between the master and slave device during
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DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. Table 2-11. DVD_CNTR_LO Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B808 FIELD /// DVDCNT[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-12. DVD_CNTR_LO Register Definitions Bits Field Name Description 15:8 /// Reserved Always returns zero. Divisor Select 7:0 DVDCNT[7:0] Selects the SPI clock rate during master mode. DVD_CNTR_HI and this
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2 2 3: I C Controller 3: I C Controller 2 This chapter describes the DSTni I C controller. Topics include: Features on page 11 Block Diagram on page 12 Theory of Operation on page 12 Programmer’s Reference on page 22 2 I C Controller Register Summary on page 22 2 I C Controller Register Definitions on page 23 Features Master or slave operation Multmaster operation Software selectable acknowledge bit Arbitration-lost interrupt with automatic mode switching from master
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Block Diagram 2 Figure 3-1 shows a block diagram of the DSTni I C controller. 2 Figure 3-1. DSTni I C Controller Block Diagram Theory of Operation 2 I C Background 2 The I C bus is a popular serial, two-wire interface used in many systems because of its low overhead. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address, with a simple master/slave protocol. 2 The I C bus consists of two wires, serial data (SDA), and a serial clock
