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®
Intel Xeon™ Processor with 800
®
MHz System Bus, Intel E7520
®
Chipset, and Intel 6300ESB ICH
Development Kit
User’s Manual
September 2004
Reference Number: 300281-003
ページ2に含まれる内容の要旨
Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
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Contents Contents 1 Product Overview ............................................................................................................................7 1.1 Related Documents ..............................................................................................................7 1.2 Product Contents ..................................................................................................................7 1.3 Products Feature List.........................................
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Contents 6.3 Level 3 Debug (Voltage References)..................................................................................34 7 Heatsink Assembly........................................................................................................................35 7.1 Processor Heat Sink Installation Instructions .....................................................................36 ® ® ® 4 Intel Xeon™ Processor, Intel E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual
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Contents Figures ® ® ® 1Intel Xeon™ Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board Block Diagram .................................................................9 2 Placement - Top View.................................................................................................................10 3 DDR2 400 Memory - DIMM Ordering .........................................................................................12 ® ® ® 4Intel Xeon™ Process
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Contents Revision History Date Revision Description Changed figures that referenced PCI-X to PCI-X 133 MHz; August 2004 003 changed jumpers on Figure 4; made other miscellaneous changes. July 2004 002 Changed code names to public names; clarified illustrations. December 2003 001 Initial release of this document. ® ® ® 6 Intel Xeon™ Processor, Intel E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual
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Product Overview Product Overview 1 ® ® ® The Intel Xeon™ Processor with 800 MHz System Bus, Intel E7520 Chipset, and Intel 6300ESB ICH Development Kit comprise an IA-32 based dual-processor platform. This platform serves as a reference for OEMs development platform. This and other development kits from Intel provide a fully working product with range of performance options which can be modified or used immediately for product development. 1.1 Related Documents Table 1. Related Documents Doc
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Product Overview 1.3 Products Feature List Processor Support ® —Dual Intel Xeon™ Processors — On-board processor voltage regulators compatible with VRM/EVRD 10.1 Design Guide Clocking — CK409B clock synthesizer that generates all host clock and the PCI Express* interface clock for the MCH PHY Layer — DB800 generates the PCI Express differential pair clocks to the onboard PCI Express components and the dedicated PCI Express slots Memory Support — Registered, ECC, DDR2 400 ® — Each of the
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Product Overview ® — Two RS-232 serial ports from the Intel 6300ESB I/O Controller — Two PS/2 connectors for mouse and keyboard — On-board VGA Video, ATI Rage Mobility* video controller — Parallel port Dual Watchdog Timer Miscellaneous — National LM93* for fan control and temperature/voltage monitoring ® Refer to Figure 1 for complete detailed features of the Intel Xeon™ Processor with 800 MHz ® ® system bus and Intel E7520 and Intel 6300ESB Customer Reference Board (CRB). 1.4 Block Diagram
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+ ++ MCH ® Intel 6300ESB I/O PXH Controller Product Overview Figure 2. Placement - Top View 1& ’ 1 &0 2 $ 1& 1 &0 1& 1 &0 ’!’ ’!’ - . * /$ 1 .. &0 %& - . * /$ 1 .. &0 *+ ,, + # *+ ,, + - . * /$ &0 () 3 " 2 !
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Product Overview 1.4.1 Memory Subsystem The memory subsystem is designed to support Double Data Rate2(DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the Intel(R) E7520 MCH. The MCH provides two independent DDR channels, which support DDR2 400 DIMMs. The peak bandwidth of each DDR2 branch channel is 3.2 Gbyte/s (8 bytes x 400 MT/s) with DDR2 400. The two DDR2 channels from the MCH operate in lock step; the effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 Gby
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Product Overview 1.5 Memory Population Rules and Configurations The system supports two DDR2 400 DIMM slots for Channel A and two DDR2 400 DIMM slots for Channel B. The four slots are interleaved and placed in a row in the following order: A1, B1, A2, B2, with A1 being closest to the MCH. This design supports only registered ECC-enabled DIMMs. When populating both channels, always place identical DIMMs in sockets that have the same position on Channel A and Channel B (i.e., DIMM A2 should be
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Platform Management Platform Management 2 The following sections describe how the system power management operates and how the different ACPI states are implemented. Platform management involves: ACPI implementation specific details System monitoring, control and response to thermal, voltage and intrusion events BIOS security 2.1 Power Button The system power button is connected to the I/O controller component. When the button is pressed, the I/O controller receives the signal and transi
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Platform Management 2.3.2 S1 State This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The system remains fully powered with memory contents intact but the processors enter their lowest power state. The operating system disables bus masters for uniprocessor configurations while flushing and invalidating caches before entering this state in multiprocessor configurations. Wake- up latency is slightly longer in this state than in S0; however, power sa
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Platform Management 2.3.6 S5 State This state is the normal off state whether entered through the Power Button or Soft Off. All power is shut off except for the logic required to restart. The system remains in the S5 State only while the power supply is plugged into the electrical outlet. If the power supply is unplugged, this is considered a Mechanical OFF or G3. 2.3.7 Wake-Up Events The types of wake-up events and wake-up latencies are related to the actual power rails available to the sys
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Platform Management 2.5.1 Processor Thermal Management Each processor monitors its own core temperature and thermally manages itself when it reaches a certain temperature. The system also uses the internal processor diode to monitor the die temperature. The diode pins are routed to the diode input pins in the LM 93. The LM 93 can be programmed to force the processor fans to full speed operation when it senses the processor core temperature exceeding a specific value. In addition, the LM 93 h
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Equipment Required for CRB Usage Equipment Required for CRB Usage 3 ® The following components are required for the Intel Xeon™ Processor with 800 MHz System ® ® Bus and Intel E7520 and Intel 6300ESB Customer Reference Board (CRB) usage: A 550 W SSI EPS 12 V power supply. The CRB is shipped with the power supply. At least two modules of DDR2 400 DIMM. The CRB is shipped with 2 x 256 Mbytes of DDR2 400. 1 Hard drive loaded with Operating System Monitor PS/2 mouse and keyboard ® Visual
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Equipment Required for CRB Usage 3.2 Driver and OS Requirements ® The required INF driver for the CRB supports the functionality of the Intel 6300ESB I/O Controller and PXH. The INF file will be included with Red Hat compatible drivers on the CD shipped with the kit. The CRB supports these operating systems: Microsoft Windows* XP, Windows Embedded XP, 2000 Pro, 2000 Server, 2000 Advanced Server, 2003 Standard Edition Red Hat Linux Advanced Server 2.1, Red Hat 8.0 on kernel 2.4.x Wind Ri
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Equipment Required for CRB Usage patches/ide-sata/pci_irq-hr-ich5.patch integrated into the ESB & ICH5 Southbridges patches/lspci/pciids-112202.patch patch to update 2.4.20 pci.ids file patches/lspci/pciids-112202-hr.patch patch to add ESB dev IDs to pci.ids patches/lspci/pciids-112202-hr-ich5.patch patch to add ICH5 dev IDs to pci.ids patches/ioapic/irqbalance-2.4.20-MRC.patch patch for use with P4 Hyper-Threading patches/smbus/i2c-hr.patch enables ESB SMBUS dev in I2C driver patches/smbus/i2c-
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Equipment Required for CRB Usage patches/ide-sata/pci_irq-hr-ich5.patch integrated into the esb6300 & ich5 southbridges patches/lspci/pci.ids-hr.patch adds esb dev ids to 2.4.9-e.24 pci.ids patches/lspci/pci.ids-hr-ich5.patch adds ich5 dev ids to 2.4.9-e.24 pci.ids patches/smbus/i2c-hr.patch enables esb smbus dev in i2c driver patches/smbus/i2c-hr-ich5.patch enables ich5 smbus dev in i2c driver patches/smbus/i2c-2.7.0-Makefile.patch customizations for i2c-2.7.0 Makefile patches/smbus/lm_sensors-
