ページ1に含まれる内容の要旨
UPI-C42/UPI-L42
UNIVERSAL PERIPHERAL INTERFACE
CHMOS 8-BIT SLAVE MICROCONTROLLER
Y Y
Pin, Software and Architecturally One 8-Bit Status and Two Data
Compatible with all UPI-41 and UPI-42 Registers for Asynchronous Slave-to-
Products Master Interface
Y Y
Low Voltage Operation with the UPI- Fully Compatible with all Intel and Most
L42 Other Microprocessor Families
Ð Full 3.3V Support
Y
Interchangeable ROM and OTP EPROM
Y
Hardware A20 Gate Support Versions
Y Y
Suspend Power Down Mode Expandable I/O
ページ2に含まれる内容の要旨
UPI-C42/UPI-L42 Table 1. Pin Description DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No. No. No. TEST 0, 1 2 18 I TEST INPUTS: Input pins which can be directly tested using conditional branch instructions. TEST 1 39 43 16 FREQUENCY REFERENCE: TEST 1 (T ) functions as the event timer 1 input (under software control). TEST 0 (T ) is a multi-function pin used 0 during PROM programming and ROM/EPROM verification, during Sync Mode to reset the instruction state to S1 and synchronize the in
ページ3に含まれる内容の要旨
UPI-C42/UPI-L42 Table 1. Pin Description (Continued) DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No. No. No. P ±P 21±24 24±27 39±42 I/O PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits 20 27 35±38 39±42 11,13±15 (P ±P ) interface directly to the 8243 I/O expander device and 20 23 contain address and data information during PORT 4±7 access. P 21 can be programmed to provide hardware A20 gate support. The upper 4 bits (P ±P ) can be programmed to provide interrupt R
ページ4に含まれる内容の要旨
UPI-C42/UPI-L42 UPI-C42/L42 PRODUCT SELECTION GUIDE UPI-C42: Low power CHMOS version of the UPI-42. Device Package ROM OTP Comments 80C42 N, P S 4K ROM Device 82C42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support 82C42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps. 82C42PE N, P, S Phoenix MultiKey/42G firmware, Energy Efficient KBC solution 87C42 N, P, S 4K One Time Programmable Version UPI-L42: The low voltage 3.3V version of the UPI-C42. Device Package
ページ5に含まれる内容の要旨
UPI-C42/UPI-L42 4. P and P are port pins or Buffer Flag pins 24 25 UPI-42 COMPATIBLE FEATURES which can be used to interrupt a master proces- sor. These pins default to port pins on Reset. 1. Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave If the ``EN FLAGS'' instruction has been execut- protocol. ed, P becomes the OBF (Output Buffer Full) 24 pin. A ``1'' written to P enables the OBF pin (the 24 pin outputs the OBF Status Bit). A ``0'' written to P
ページ6に含まれる内容の要旨
UPI-C42/UPI-L42 If ``EN DMA'' has been executed, P becomes 27 PROGRAM MEMORY BANK SWITCH the DACK (DMA ACKnowledge) pin. This pin acts as a chip select input for the Data Bus Buffer The switching of 2K program memory banks is ac- registers during DMA transfers. complished by directly setting or resetting the most significant bit of the program counter (bit 11); see EN DMA Op Code: 0E5H Figure 5. Bit 11 is not altered by normal increment- ing of the program counter, but is loaded with the 1 11001
ページ7に含まれる内容の要旨
UPI-C42/UPI-L42 thereby providing additional user programmable SUSPEND memory space. This feature is enabled by the A20EN instruction and remains enabled until the de- The execution of the suspend instruction (82h or vice is reset. It is important to note that the execu- E2h) causes the UPI-C42 to enter the suspend tion of the A20EN instruction redefines Port 2, bit 1 mode. In this mode of operation the oscillator is not as a pure output pin with read only characteristics. running and the intern
ページ8に含まれる内容の要旨
UPI-C42/UPI-L42 Table 2 covers all suspend mode pin states. In addi- NEW UPI-C42 INSTRUCTIONS tion to the suspend power down mode, the UPI-C42 will also support the NMOS power down mode as The UPI-C42 will support several new instructions to outlined in Chapter 4 of the UPI-42AH users manual. allow for the use of new C42 features. These in- structions are not necessary to the user who does Table 2. Suspend Mode Pin States not wish to take advantage of any new C42 function- ality. The C42 will be
ページ9に含まれる内容の要旨
UPI-C42/UPI-L42 This circuitry gives the host direct control of port 2 Pin Function bit 1 (P2.1) without intervention by the internal CPU. When this opcode is executed, P2.1 becomes a ded- XTAL 2 Clock Input icated output pin. The status of this pin is read-able Reset Initialization and Address Latching but can only be altered through a valid ``D1'' com- mand sequence (see Table 1). Test 0 Selection of Program or Verify Mode EA Activation of Program/Verify Signature SUSPEND Invoke Suspend Power
ページ10に含まれる内容の要旨
UPI-C42/UPI-L42 flow chart of the Quick-Pulse Programming Algo- rithm is shown in Figure 6. The entire sequence of program pulses and byte e verifications is performed at V 6.25V and CC e V 12.75V. When programming has been com- DD pleted, all bytes should be compared to the original e e data with V V 5V. CC DD A verify should be performed on the programmed bits to ensure that they have been correctly pro- e grammed. The verify is performed with T0 5V, e e Ý e e V 5V, EA 12.75V, SS 5V, PROG 5V,
ページ11に含まれる内容の要旨
UPI-C42/UPI-L42 b. Apply access code to appropriate inputs to put and will be present in the ROM and OTP ver- the device into security mode. sions. Location 10H contains the manufacturer code. For Intel, it is 89H. Location 11H contains c. Apply high voltage to EA and V pins. DD the device code. d. Follow the programming procedure as per the The code is 43H and 42H for the 8042AH/80C42 Quick-Pulse Programming Algorithm with known and OTP 8742AH/87C42, respectively. The data on the databus. Not o
ページ12に含まれる内容の要旨
UPI-C42/UPI-L42 Table 3. Signature Mode Table Device No. of Address Type Bytes Test Code/Checksum 0 0FH ROM/OTP 25 16H 1EH Intel Signature 10H 11H ROM/OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM/OTP 2 Security Byte 1FH or 3FH ROM/OTP 2 UPI-C42 Intel Signature 20H 21H ROM/OTP 2 User Defined UPI-C42 OTP EPROM Space 22H 3EH ROM/OTP 30 ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode, and the Security Bit, respectively. Al
ページ13に含まれる内容の要旨
UPI-C42/UPI-L42 SYNC MODE TIMING DIAGRAMS 290414±15 Minimum Specifications e e SYNC Operation Time, t 3.5 XTAL 2 Clock cycles. Reset Time, t 4t . SYNC RS CY NOTE: The rising and falling edges of T0 should occur during low state of XTAL 2 clock. APPLICATIONS 290414±12 Figure 7. UPI-C42 Keyboard Controller 290414±9 Figure 8. 8088-UPI-C42 Interface 13
ページ14に含まれる内容の要旨
UPI-C42/UPI-L42 APPLICATIONS (Continued) 290414±10 Figure 9. 8048H-UPI-C42 Interface 290414±11 Figure 10. UPI-C42-8243 Keyboard Scanner 290414±13 Figure 11. UPI-C42 80-Column Matrix Printer Interface 14
ページ15に含まれる内容の要旨
UPI-C42/UPI-L42 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. a Ambient Temperature Under Bias ÀÀÀÀ0 Cto 70 C § § *WARNING: Stressing the device beyond the ``Absolute b a Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 Cto 150 C § § Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the Voltage on Any Pin with ``Operating Conditions'' is not recommended and ex- b a Respect to GroundÀÀÀÀÀÀ
ページ16に含まれる内容の要旨
UPI-C42/UPI-L42 DC CHARACTERISTICS e a e ea a T 0Cto 70 C, V V 5V g10%; 3.3V g10% UPI-L42 (Continued) § § A CC DD UPI-C42 UPI-L42 Symbol Parameter Units Notes Min Max Min Max a I I Total Supply Current: CC DD @ Active Mode 12.5 MHz 30 20 mA Typical 14 mA UPI-C42, 9 mA UPI-L42 (1, 4) Suspend Mode 40 26 mA Osc. Off I Standby Power Down 5 3.5 mA NMOS Compatible DD Power Down Mode Supply Current e I Input Leakage Current 100 100 mAV V IH IN CC (P ±P ,P ±P ) 10 17 20 27 e (1) C Input Capacitance 10 1
ページ17に含まれる内容の要旨
UPI-C42/UPI-L42 AC CHARACTERISTICS e a e e ea a T 0Cto 70 C, V 0V, V V 5V g10%; 3.3V g10% for the UPI-L42 § § A SS CC DD NOTE: All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Min Max Units t CS, A Setup to RDv 0ns AR 0 t CS, A Hold After RDu0ns RA 0 t RD Pulse Width 160 ns RR t CS, A to Data Out Delay 130 ns AD 0 t RDv to Data Out Delay 0 130 ns RD t RD to Data Float Delay 85 ns u DF DBB WRITE Symbol Parameter Min Max Units t CS, A Setup to WR 0ns v AW 0 t
ページ18に含まれる内容の要旨
UPI-C42/UPI-L42 AC CHARACTERISTICS e a e e ea a T 0Cto 70 C, V 0V, V V 5V g10%; 3.3V g10% for the UPI-L42 (Continued) § § A SS CC DD CLOCK Symbol Parameter Min Max Units (1) t UPI-C42/UPI-L42 Cycle Time 1.2 9.20 ms CY t UPI-C42/UPI-L42 Clock Period 80 613 ns CYC t Clock High Time 30 ns PWH t Clock Low Time 30 ns PWL t Clock Rise Time 10 ns R t Clock Fall Time 10 ns F NOTE: e 1. t 15/f(XTAL) CY AC CHARACTERISTICS DMA Symbol Parameter Min Max Units t DACK to WR or RD 0 ns ACC t RD or WR to DACK 0
ページ19に含まれる内容の要旨
UPI-C42/UPI-L42 AC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42) e e ea e T 25 C g5 C, V 6.25V g0.25V, V 5V g0.25V, V 12.75V g0.25V § § A CC DDL DDH (87C42/87L42 ONLY) Symbol Parameter Min Max Units t Address Setup Time to RESETu 4t AW CY t Address Hold Time after RESETu 4t WA CY t Data in Setup Time to PROGv 4t DW CY t Data in Hold Time after PROGu 4t WD CY t Initial Program Pulse Width 95 105 ms PW t Test 0 Setup Time for Program Mode 4t TW CY t Test 0 Hold Time after Program Mode 4t WT CY
ページ20に含まれる内容の要旨
UPI-C42/UPI-L42 DRIVING FROM AN EXTERNAL SOURCE 290414±18 290414±19 Rise and Fall Times Should Not NOTE: Exceed 10 ns. Resistors to V CC See XTAL1 Configuration Table. e are Needed to Ensure V 3.5V IH if TTL Circuitry is Used. LC OSCILLATOR MODE CRYSTAL OSCILLATOR MODE L C NOMINAL 1 e 45 H 20 pF 5.2 MHz f 2q LC 0 Ê 120 H 20 pF 3.2 MHz C a 3Cpp e CÊ 2 290414±21 C1 5 pF (STRAY 5 pF) j Cpp 5±10 pF a C2 (CRYSTAL STRAY) 8 pF Pin-to-Pin Capacitance C3 20±30 pF INCLUDING STRAY Crystal Series Resistance
