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®
Intel IXP43X Product Line of
Network Processors
Hardware Design Guidelines
April 2007
Document Number: 316844; Revision: 001US
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors Contents 1.0 Introduction ..............................................................................................................9 1.1 Content Overview................................................................................................9 1.2 Related Documentation ...................................................................................... 10 1.3 Acronyms.......................................
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines 3.14 Power ..............................................................................................................52 3.14.1 Decoupling Capacitance Recommendations.................................................53 3.14.2 VCC Decoupling......................................................................................53 3.14.3 VCC33 Decoupling ....................................................................
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors 11 HSS Interface Example ............................................................................................. 42 12 Serial Flash and SSP Port (SPI) Interface Example........................................................ 44 13 PCI Interface........................................................................................................... 47 14 Clock Oscillator Interface Example.........................
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines 29 DDR Clock Timings ...................................................................................................75 30 DDRII-400 MHz Interface -- Signal Timings..................................................................77 31 DDR II/I SDRAM Interface -- Signal Timings.................................................................78 32 Timing Relationships...................................................
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors Revision History Date Revision Description April 2007 001 Initial release § § ® Intel IXP43X Product Line of Network Processors April 2007 HDG Document Number: 316844; Revision: 001US 7
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines ® Intel IXP43X Product Line of Network Processors HDG April 2007 8 Document Number: 316844; Revision: 001US
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors 1.0 Introduction This design guide provides recommendations for hardware and system designers who ® are developing with the Intel IXP43X Product Line of Network Processors. This ® document should be used in conjunction with the Intel IXP43X Product Line of ® Network Processors Datasheet and sample schematics provided for the Intel IXP435 Multi-Service Residential Gateway Reference Platform. Design recommendations ar
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines 1.2 Related Documentation The reader of this design guide should also be familiar with the material and concept presented in the following documents: Title Document # ® Intel IXP43X Product Line of Network Processors Datasheet 316842 ® Intel IXP43X Product Line of Network Processors Developer’s 316843 Manual ® Intel IXP43X Product Line of Network Processors: Migrating from 316845 ® the Intel IXP42X Product Line ® In
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors Table 1. List of Acronyms and Abbreviations (Sheet 2 of 2) Term Explanation PMU Performance Monitoring Unit SME Small-to-Medium Enterprise SSP Synchronous Serial Protocol UART Universal Asynchronous Receiver-Transmitter USB Universal Serial Bus VTT Termination Voltage Supply 1.4 Overview ® The Intel IXP43X Product Line of Network Processors is a highly integrated device, capable of interfacing with most common industry
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines • 16 GPIO (General Purpose Input Output) •Packaging —460-pin PBGA — 31 mm by 31 mm — Commercial temperature (0° to 70° C) — Lead free support ® Refer to the Intel IXP43X Product Line of Network Processors Datasheet for complete feature list and block diagram description. Note: 1. This feature requires Intel-supplied software. To determine if this feature is enabled ® in a particular software release, refer to the Inte
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors ® Figure 1. Intel IXP435 Network Processor Block Diagram HSS UTOPIA 2/ MII NPE A NPE C North AHB 133. 32 MHz x 32 bits MII AES/ 3DES/ DES/ North AHB SHA/ MD-5 Arbiter SSP High Speed UART 921 Kbaud 16 GPIO GPIO 16/32 BITS + ECC AHB Interrupt DDR 266 / Slave / DDRII/ I MEMORY Controller APB QUEUE AHB/ AHB CONTROLLER DDRII 400 MANAGER BRIDGE UNIT Master 266/ 400 BRIDGE IBPMU South AHB 133. 32 MHz x 32 bits South
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines 1.5 Typical Applications • SOHO-Small Business/Residential • Modular Router • Wireless Gateway(802.11a/b/g) • Network-Attached Storage • Wired/Wireless RFID Readers • Digital Media Adapter • Digital Media Player •VoIP Router •Video Phone • Secure Gateway/Router •Network Printer • Wireless Media Gateway • IP Set Top box § § ® Intel IXP43X Product Line of Network Processors HDG April 2007 14 Document Number: 316844; Revi
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors 2.0 System Architecture 2.1 System Architecture Description ® The Intel IXP43X Product Line of Network Processors is a multifunction processor that ® integrates the Intel XScale Processor (ARM* architecture compliant) with highly integrated peripheral controllers and network processor engines. The processor is a highly integrated design, manufactured with Intel’s 0.13-µm production semiconductor process technology. T
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PCI Slots DDRII/I SDRAM Memory Bus cPCI J1 cPCI J2 ® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines ® Figure 2. Example: Intel IXP43X Product Line of Network Processors System Block Diagram JTAG Header DDR DDR Flash CB[7:0] DDR SDRAM SDRAM 32 Mbyte SDRAM D[31:0] 16Mx4x16 DDRII/I 16Mx4x16 CS_N0 16Mx4x16 512 Mbyte SDRAM BA[1:0] 512 Mbyte 512 Mbyte (Four Chips) Max 1 Gbyte (Four Chips) D[15:0] A[13:0] (Four Chips) RAS, CAS, WE, CS,CLK Board A[23:0] Configuration Reset
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors 3.0 General Hardware Design Considerations This chapter contains information for implementing and interfacing with major ® hardware blocks of the Intel IXP43X Product Line of Network Processors. Such blocks include DDRII/I SDRAM, Flash, Ethernet PHYs, UART and other peripherals interfaces. Signal definition tables list resistor recommendations for pull-ups and pull-downs. Features disabled by a specific part number,
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines Table 3. Soft Fusible Features (Sheet 2 of 2) Name Description ETHERNET Can enable MII MACs. Enable of MACs can be separately done per each NPE. USB Host Each USB can be Enable separately. DDR ECC ECC can be enabled or disabled separately from the rest of the DDR interface. 3.2 DDRII/I SDRAM Interface The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM technology, capable of addressing two mem
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® Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked when the data is read. If the code is incorrect, the MCU corrects the data before reaching the initiator of the read. ECC error scrubbing is done with software. User-defined fault correction software is responsible for The value written back into the memory lo
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® Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2) VTT Type Name Device-Pin Connection Terminatio Description Field n ECC Bus — Eight-bit error correction code which accompanies the data on D_DQ[31:0]/ DDR_DQ[31:0]. D_CB[7:0] / I/O Connect to ECC memory devices. Yes DDR_CB[7:0] When ECC is disabled and not being used in a system design, these signals can be left un- connected. Data Strobes Differential
