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® ™
Desktop 4th Generation Intel Core
®
Processor Family, Desktop Intel
®
Pentium Processor Family, and
® ®
Desktop Intel Celeron Processor
Family
Datasheet – Volume 1 of 2
December 2013
Order No.: 328897-004
ページ2に含まれる内容の要旨
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHA
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Contents—Processor Contents Revision History..................................................................................................................9 1.0 Introduction................................................................................................................10 1.1 Supported Technologies.........................................................................................11 1.2 Interfaces.............................................................................
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Processor—Contents 4.2.3 Requesting Low-Power Idle States...............................................................53 4.2.4 Core C-State Rules....................................................................................54 4.2.5 Package C-States......................................................................................55 4.2.6 Package C-States and Display Resolutions....................................................59 4.3 Integrated Memory Controller (IMC) Power Managemen
ページ5に含まれる内容の要旨
Contents—Processor 7.0 Electrical Specifications.............................................................................................. 90 7.1 Integrated Voltage Regulator..................................................................................90 7.2 Power and Ground Lands ...................................................................................... 90 7.3 V Voltage Identification (VID).............................................................................. 90 CC 7
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Processor—Figures Figures 1 Platform Block Diagram ...........................................................................................11 ® 2 Intel Flex Memory Technology Operations.................................................................21 3 PCI Express* Related Register Structures in the Processor............................................ 25 4 PCI Express* Typical Operation 16 Lanes Mapping....................................................... 26 5 Processor Graphics Controll
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Tables—Processor Tables 1 Terminology........................................................................................................... 13 2 Related Documents..................................................................................................16 3 Processor DIMM Support by Product...........................................................................19 4 Supported UDIMM Module Configurations....................................................................19 5 Support
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Processor—Tables 54 GTL Signal Group and Open Drain Signal Group DC Specifications................................ 102 55 PCI Express* DC Specifications................................................................................103 56 Platform Environment Control Interface (PECI) DC Electrical Limits...............................103 57 Processor Loading Specifications..............................................................................106 58 Package Handling Guidelines.............
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Revision History—Processor Revision History Revision Description Date 001 • Initial Release June 2013 ® ™ • Added Desktop 4th Generation Intel Core i7-4771, i5-4440, i5-4440S, i3-4340, i3-4330, i3-4330T, i3-4130, and i3-4130T processors ® ® • Added Desktop Intel Pentium G3430, G3420, G3220, 002 September 2013 G3420T, G3220T processors • Updated Section 4.2.4, Core C-State Rules • Updated Section 4.2.5, Package C-States • Minor edits throughout for clarity 003 • Minor edits throughout for clarity
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Processor—Introduction 1.0 Introduction ® ™ ® ® The Desktop 4th Generation Intel Core processor family , Desktop Intel Pentium ® ® processor family, and Desktop Intel Celeron processor family are 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform consisting of a processor and ® Platform Controller Hub (PCH). The processors are designed to be used with the Intel 8 Series chipset. See the following figure for an example platf
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Introduction—Processor Figure 1. Platform Block Diagram 1333 / 1600 MT/s PCI Express* 3.0 2 DIMMs / CH CH A Processor Digital Display System Memory CH B Interface (DDI) (3 interfaces) Note: 2 DIMMs / CH is not supported on all SKUs. ® Intel Flexible Display Direct Media Interface 2.0 ® Interface (Intel FDI) (DMI 2.0) (x4) (x2) USB 3.0 Analog Display (up to 6 Ports) (VGA) USB 2.0 Integrated LAN (8 Ports) Platform Controller Hub (PCH) SATA, 6 GB/s PCI Express* 2.0 (up to 6 P
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Processor—Introduction • PCLMULQDQ Instruction ® • Intel Secure Key ® ® • Intel Transactional Synchronization Extensions - New Instructions (Intel TSX- NI) • PAIR – Power Aware Interrupt Routing • SMEP – Supervisor Mode Execution Protection Note: The availability of the features may vary between processor SKUs. 1.2 Interfaces The processor supports the following interfaces: • DDR3/DDR3L • Direct Media Interface (DMI) • Digital Display Interface (DDI) • PCI Express* 1.3 Power Management Support
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Introduction—Processor 1.4 Thermal Management Support • Digital Thermal Sensor • Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS 1.5 Package Support The processor socket type is noted as LGA1150. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1150). See the appropriate P
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Processor—Introduction Term Description ECC Error Correction Code eDP* embedded DisplayPort* EPG Electrical Power Gating EU Execution Unit FMA Floating-point fused Multiply Add instructions FSC Fan Speed Control HDCP High-bandwidth Digital Content Protection HDMI* High Definition Multimedia Interface HFM High Frequency Mode iDCT Inverse Discrete IHS Integrated Heat Spreader GFX Graphics GSA Graphics in System Agent GUI Graphical User Interface IMC Integrated Memory Controller ® Intel 64 64-bit m
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Introduction—Processor Term Description MLC Mid-Level Cache MSI Message Signaled Interrupt MSL Moisture Sensitive Labeling MSR Model Specific Registers Non-Critical to Function. NCTF locations are typically redundant ground or non-critical NCTF reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. ODT On-Die Termination OLTM Open Loop Thermal Management Platform Compatibility Guide (PCG) (previously known as FMB) provide
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Processor—Introduction Term Description TAP Test Access Point The case temperature of the processor, measured at the geometric center of the top- T CASE side of the TTV IHS. TCC Thermal Control Circuit T is a static value that is below the TCC activation temperature and used as a CONTROL T trigger point for fan speed control. When DTS > T , the processor must comply CONTROL CONTROL to the TTV thermal profile. Thermal Design Power: Thermal solution should be designed to dissipate this target TDP
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Introduction—Processor Document Document Number / Location LGA1150 Socket Application Guide 328999 ® Intel 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) 328904 Datasheet ® Intel 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) 328905 Specification Update ® Intel 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) Thermal 328906 Mechanical Specifications and Design Guidelines http:// Advanced Configuration and Power Interface 3.0 www.acpi.i
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Processor—Interfaces 2.0 Interfaces 2.1 System Memory Interface • Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM) or DDR3/DDR3L Unbuffered Small Outline Dual In-Line Memory Modules (SO- DIMM) with a maximum of two DIMMs per channel. • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • Memory data transfer rates of 1333 MT/s and 1600 MT/s • 64-bit wide channels • DDR3/DDR3L I/O Voltage of 1.5 V for
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Interfaces—Processor 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependent on the PCH SKU in the target platform. Note: The IMC supports a maximum of two DDR3/DDR3L DIMMs per channel; thus, allowing up to four device ranks per channel. Note: The support of DDR3/DDR3L frequencies and number of DIMMs per chan
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Processor—Interfaces Raw DIMM DRAM DRAM # of # of # of # of Page Size Card Capacity Device Organization DRAM Physical Row / Col Banks Version Technology Devices Devices Address Inside Ranks Bits DRAM 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K B 4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K 8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K Note: DIMM module support is based on availability and is subject to change. Table 5. Supported SO-DIMM Module Configurations (AIO Only) Raw Card DIMM DRAM
