ページ15に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 6. Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected Registers Problem: The instruction decoder incorrectly decodes the valid combination of P=0, U=1 and W=0, when using unindexed mode in addressing mode 5 (load and store coprocessor). In this case, the LDC or STC should produce consecutive address loads or stores, with no base update until the coprocessor signals that it has received enough data. Instea
ページ16に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 10. Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty Problem: When there is an aborted store that hits clean data in the data cache (data in an aligned four word range, that has not been modified from the core, since it was last loaded in from memory or cleaned), the data in the array is not modified (the store is blocked), but the dirty bit is set. When the line is then aged out of the data cache or explicitly clea
ページ17に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 11. Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated Events Problem: Event 0x1 in the performance monitor unit (PMU) can be used to count cycles in which the instruction cache cannot deliver an instruction. The only cycles counted should be those due to an instruction cache miss or an instruction TLB miss. The following unrelated events in the core, also causes the corresponding count to increment when even
ページ18に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 13. Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values Problem: The ARM Architecture Reference Manual (ARM DDI 0100E) states the following in chapter B-2, section 2.3: “If an value corresponding to an unimplemented or reserved ID register is encountered, the System Control processor returns the value of the main ID register. ID registers other than the main ID register are defined so that when i
ページ19に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 15. Updating the JTAG parallel register requires an extra TCK rising edge Problem: IEEE 1149.1 states that the effects of updating all parallel JTAG registers should be seen on the ® falling edge of TCK in the Update-DR state. The Intel Xscale core parallel JTAG registers incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like hold-reset, JTAG break, and vector traps require either an extra TCK
ページ20に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Non-Core Errata Non-Core Errata 1. The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when Using 32-Bit Memory, ECC Enabled and in PCI Mode The external PCI bus requests a read through the ATU to the MCU, starting at the high DWORD. Remember the MCU is in 32-bit mode. The ATU requests multiple DWORDs since it pre-fetches, but starts at the high DWORD address. The MCU issues two DWORDs. First the high, followed by the low an
ページ1に含まれる内容の要旨
®
Intel 80219 General Purpose PCI
Processor
Specification Update
July 2004
®
Notice: The Intel 80219 General Purpose PCI Processor (80219) may contain design defects or
errors known as errata that may cause the product to deviate from published specifications.
Current characterized errata are documented in this specification update.
Document Number: 274020-002
ページ2に含まれる内容の要旨
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
ページ3に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 6 Summary Table of Changes....................................................................... 7 Identification Information...........................................................................11 Core Errata ...........
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® Intel 80219 General Purpose PCI Processor This Page Left Intentionally Blank 4 Specification Update
ページ5に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Revision History Revision History Date Version Description July 2004 002 Added Specification Clarification 7. November 2003 001 Initial Release. Specification Update 5
ページ6に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Preface Preface This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and
ページ7に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or ® documentation changes which apply to the Intel 80219 General Purpose PCI Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notati
ページ8に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Summary Table of Changes Core Errata Steppings No. Page Status Errata A-0 1 X 13 NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification 2 X 13 NoFix Drain Is Not Flushed Correctly when Stalled in the Pipeline 3 X 14 NoFix Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction 4 X 14 NoFix Debug Unit Synchronization with the TXRXCTRL Register 5 X 14 NoFix Extra Circuitry Is Not JTAG Boundary Scan Complia
ページ9に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Summary Table of Changes Non-Core Errata Steppings No. Page Status Errata A-0 The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when 1 X 20 NoFix Using 32-Bit Memory, ECC Enabled and in PCI Mode 2 X 20 NoFix PBI Issue When Using 16-bit PBI Transactions in PCI Mode 3 X 21 NoFix MCU Pointers are Incorrect following a Restoration from a Power Fail PMU Does Not Account for when the Arbiter Deasserts GNT# One Cycle before 4 X 21
ページ10に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Summary Table of Changes Specification Changes Steppings No. Page Specification Changes A-0 1 X 24 Signal NC2 was renamed to P_BMI (AE23). New function added to signal P_BMI. Specification Clarifications Steppings No. Page Status Specification Clarifications A-0 ® The Intel 80219 general purpose PCI processor is compliant with the PCI Local Bus 1 X 26 NoFix Specification, Revision 2.2 but it is not compliant with PCI Local Bus Specification, Revisio
ページ11に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Identification Information Identification Information Markings Figure 1. Topside Markings FW80219Mxxx {FPO#} SLxxx INTEL © ‘2001 M ® Intel 80219 General Purpose PCI Processor Specification Update 11
ページ12に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Identification Information Die Details ® Intel 80219 General QDF (Q)/ Stepping Part Number Voltage (V) Purpose PCI Processor Notes Specification Number (SL) Speed (MHz) A-0 FW80219M400 Q690 3.3 400 Samples A-0 FW80219M600 Q691 3.3 600 Samples A-0 FW80219M400 SL7CL 3.3 400 Production Material A-0 FW80219M600 SL7CM 3.3 600 Production Material Device ID Registers Processor Device ID ATU Device ID ATU Revision ID Device and Stepping JTAG Device ID (CP15,
ページ13に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata Core Errata 1. Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification Problem: The IEEE Standard 1149.1 specifies the boundary scan logic to support two main goals: 1. To allow the interconnections between the various components to be tested, test data can be shifted into all the boundary-scan register cells associated with component output pins and loaded in parallel through the component interconnections, into those cells
ページ14に含まれる内容の要旨
® Intel 80219 General Purpose PCI Processor Core Errata 3. Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction Problem: The instruction decode allows undefined opcodes, which look similar to the MSR (Move to Status register from an ARM register) instruction, to be interpreted as an MSR instruction. The mis-decoded MSR instruction also adds a SUBNV PC,0x4 to the instruction flow. Workaround: Do not use undefined opcodes of this form: 3130292827262524232221201918
