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80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Datasheet
Product Features
32-Bit Parallel Architecture 3.3 V Supply Voltage
—Load/Store Architecture —5 V Tolerant Inputs
—Sixteen 32-Bit Global Registers —TTL Compatible Outputs
—Sixteen 32-Bit Local Registers Guarded Memory Unit
—Provides Memory Protection
—1.28 Gbyte Internal Bandwidth
(80 MHz)
—User/Supervisor Read/Write/Execute
—On-Chip Register Cache
32-Bit Demultiplexed Burst Bus
Processor Core Clock
—Per-Byte Parit
ページ2に含まれる内容の要旨
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ページ3に含まれる内容の要旨
Contents Contents 1.0 About This Document ...................................................................................................................9 2.0 Intel 80960Hx Processor ...............................................................................................................9 ® 2.1 The i960 Processor Family ...............................................................................................10 2.2 Key 80960Hx Features .............................................
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Contents 7 VCC5 Current-Limiting Resistor .................................................................................................38 8 AC Test Load..............................................................................................................................45 9 CLKIN Waveform........................................................................................................................46 10 Output Delay Waveform ...................................................
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Contents 57 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................81 58 Idle Bus Operation......................................................................................................................82 59 Bus States ..................................................................................................................................83 Tables 1 80960Hx Product Description...................................................
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Contents Revision History Date Revision History Formatted the datasheet in a new template. In “32-Bit Parallel Architecture” on page 1: • Removed operating frequency of 16/32 (bus/core) from 80960HD. • Removed operating frequency of 20/60 (bus/core) from 80960HT. In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14: • Removed core speed of 32 MHz and bus speed of 16 MHz, and order number A80960HD32-S-L2GG from the 168L PGA package, 80960HD device. September 2002 008 • Removed core s
ページ7に含まれる内容の要旨
Contents Date Revision History In Table 23 “80960Hx AC Characteristics” on page 42: • Added overbars where required. • Modified T to list separate specifications for 3.3 V and 5 V. DVNH • Modified T , T and T to reflect specific 80960HA, 80960HD OV2 OH2 TVEL and 80960HT values. July 1998 007 (continued) (continued) In Figure 23 “ICC Active (Power Supply) vs. Frequency” on page 51: • Changed ‘5’ to ‘0’ on the CLKIN Frequency axis. In Figure 49 “BREQ and BSTALL Operation” on page 74: • Added fig
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Contents This page intentionally left blank. 8 Datasheet
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80960HA/HD/HT 1.0 About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics, other than parametric performance, ® are published in the i960 Hx Microprocessor User’s Guide (272484). In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table 1. Throughout this document, information that is specific to each is clearly indicated. Figure 1. 80960Hx Bl
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80960HA/HD/HT In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan test and
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80960HA/HD/HT subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently. The Bus Controller’s key features include: • Demultiplexed, Burst Bus to support most efficient DRAM access modes • Address Pipelining to reduce memory cost while maintaining performance • 32-, 16- and 8-bit modes to facilitate I/O interfacing • Full internal w
ページ12に含まれる内容の要旨
80960HA/HD/HT 2.2.6 Dual Programmable Timers The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers through the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the processor’s interrupt controller. 2.2.7 Processor Self Test W
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80960HA/HD/HT 2.3 Instruction Set Summary Table 4 summarizes the 80960Hx instruction set by logical groupings. Table 4. 80960Hx Instruction Set Data Movement Arithmetic Logical Bit / Bit Field / Byte Add Subtract Multiply And Set Bit Divide Not And Clear Bit Remainder And Not Not Bit Load Modulo Or Alter Bit Store Shift Exclusive Or Scan For Bit Move Extended Shift Not Or Span Over Bit Load Address Extended Multiply Or Not Extract 2 Conditional Select Extended Divide Nor Modify Add with Carry E
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80960HA/HD/HT 3.0 Package Information This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# 240800). The 80960HA/HD/HT is offered with eight speeds and two package types (Table 5). Both the 168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified for ope
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80960HA/HD/HT 3.1 Pin Descriptions This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin descriptions in Table 7. All pins float while the processor is in the ONCE mode, except TDO, which may be driven active according to normal JTAG specifications. Table 6. Pin Description Nomenclature Symbol Description I Input only pin. O Output only pin. I/O Pin may be input or output. - Pin must be connected as indicated for proper device functionality. Synchronous e
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80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4) Name Type Description ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most O significant address bit and A2 is the least significant. During a bus access, A31:2 H(Z) A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable B(Z) signals indicate the selected byte in each word. During burst accesses, A3 and R(Z) A2 increment to indicate successive addresses. I/O
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80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4) Name Type Description SUPERVISOR ACCESS indicates whether the current bus access originates O from a request issued while in supervisor mode or user mode. SUP may be used by the memory subsystem to isolate supervisor code and data structures from H(Z) SUP non-supervisor access. B(Z) R(1) 0 = Supervisor Mode 1 = User Mode O ADDRESS STROBE indicates a valid address and the start of a new bus access. H(Z) ADS ADS
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80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4) Name Type Description HOLD REQUEST signals that an external agent requests access to the processor’s address, data, and control buses. When HOLD is asserted, the processor: I Completes the current bus request. HOLD S(L) Asserts HOLDA and floats the address, data, and control buses. When HOLD is deasserted, the HOLDA pin is deasserted and the processor reassumes control of the address, data, and control pins. O H
ページ19に含まれる内容の要旨
80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4) Name Type Description CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is synchronized to CLKIN. All input and output timings are specified relative to CLKIN. CLKIN I For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying the CLKIN frequency by three. RESET forces the device into res
ページ20に含まれる内容の要旨
80960HA/HD/HT 3.2 80960Hx Mechanical Data 3.2.1 80960Hx PGA Pinout Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960Hx PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). Table 9 lists the 80960Hx pin names with package location. See Section 4.3, “Recommended Connections” on page 38 for specifications and recommended connections. Figure 2. 80960Hx 168-Pin PGA Pin
