ページ1に含まれる内容の要旨
ICP-PIII
High-Performance
CPU Boards
USER’S MANUAL
Publication Number: PD00581013.004 AB
MAN-ICP-PIII
®
CompactPCI
ページ2に含まれる内容の要旨
This user’s manual describes a product that, due to its nature, cannot describe a particular applica- tion. The content of this user’s manual is furnished for informational use only, is subject to change without notice, and should not be constructed as a commitment by Inova Computers GmbH. Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user’s manual. Except as otherwise agreed, no part of this publication may be reproduced, stor
ページ3に含まれる内容の要旨
ICP-PIII Preface Preface Contents Unpacking and Special Handling Instruc- tions............................................... 6 Revision History ............................... 7 Three Year Limited Warranty.............. 8 1.0 ICP-PIII CPU ........................... 1-2 1.01 Interfacing ............................................................................................... 1-3 1.02 Peripherals .............................................................................................
ページ4に含まれる内容の要旨
Preface ICP-PIII 1.4 Hardware ............................. 1-10 1.41 Block Diagram........................................................................................ 1-10 Figure 1.41 Block Diagram....................................................................................................... 1-10 1.42 Connector Location ............................................................................... 1-11 Figure 1.42 Connector Locations ................................................
ページ5に含まれる内容の要旨
ICP-PIII Preface 3.1 CompactPCI Backplane .......... 3-10 Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ................................ 3-11 3.2 Interfaces............................. 3-12 3.21 J7 & J12 Fast Ethernet ............................................................................ 3-12 Figure 3.21 RJ45 Pinout ........................................................................................................... 3-12 Table 3.21 Ethernet Connector Signal
ページ6に含まれる内容の要旨
Preface ICP-PIII A1 IPB-FPE8 CPU Extension ......... A-2 A1.1 J11 Interface for COM1, Mouse & Keyboard ............................................ A-2 A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)....................................................... A-2 Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU .......................................................... A-2 A1.3 Stand-Alone IPB-FPE8 ............................................................................... A-3 Figure A1.3 Stand-A
ページ7に含まれる内容の要旨
ICP-PIII Preface B1 IPM-ATA CPU Extension ........... B-2 B1.1 J1 Interfaces ............................................................................................. B-2 Figure B1.1a Dedicated IPM-ATA Backplane................................................................................ B-2 B1.1 J1 Interfaces (Contd.) ............................................................................... B-3 Figure B1.1b The Complete Connection Picture............................................
ページ8に含まれる内容の要旨
Preface ICP-PIII Unpacking and Special Handling Instructions This product has been designed for a long and fault-free life; nonetheless, its life expectancy can be severely reduced by improper treatment during unpacking and installation. Observe standard antistatic precautions when changing piggybacks, ROM devices, jumper set- tings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not placed on conductive surfaces as these can cause short circuits, damage
ページ9に含まれる内容の要旨
ICP-PIII Preface Revision History Revision History Manual MAN-ICP-PIII Publication Number PD00581013.XXX Date of Issue Issue Brief Description of Changes Author PD00581013.001 Preliminary, First Release; All pages revised AB 31/11/2000 PD00581013.002 Updated to include Radeon VE and Rear I/O options AB 15/08/2001 PD00581013.003 Final Version - Included Appendix A-D I/O Modules AB 21/09/2001 PD00581013.004 Specs. Updated & Rear I/O Table Corrected AB 15/02/2002 Doc. PD00581013.004 ©2002 Inova Com
ページ10に含まれる内容の要旨
Preface ICP-PIII Three Year Limited Warranty Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova. Inova warrants their own products (excluding software) to be free from defects in workmanship and materials for a period of 36 consecutive months from the date of purchase. This warranty is not t
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ICP-PIII Product Overview 1 Product Overview Overview Contents 1.0 ICP-PIII CPU ........................... 1-2 1.01 Interfacing ............................................................................................... 1-3 1.02 Peripherals ............................................................................................... 1-3 1.03 Software .................................................................................................. 1-3 1.04 Graphics .......................
ページ12に含まれる内容の要旨
Product Overview ICP-PIII 1.0 ICP-PIII CPU The ICP-PIII is a high-performance 3U CompactPCI single-board Socket 370 based universal CPU that satisfies the needs of a wide range of industrial automation, military, medical, aerospace, imaging, telecommunications, process control and embedded/OEM applications. The powerhouse in any application, Inova’s Socket 370 based high-performance 3U CompactPCI CPU is packed with a feature set unheard of on such a small scale. With 128MByte on-board SDRAM with
ページ13に含まれる内容の要旨
ICP-PIII Product Overview 1.01 Interfacing For maximum communication flexibility, multiple interfaces satisfying different industrial stand- 1 ards are implemented. LAN applications can take advantage of Inova’s 10BaseT/100BaseTx (dual) Ethernet implementation or, if high-speed system-level serial interfacing is required, the built-in 400/100 Mbit/s FireWire port is available. Peripherals may be connected to the standard USB or, as an option, the on-board PCI bus allows support of custom I/O pig
ページ14に含まれる内容の要旨
Product Overview ICP-PIII 1.1 Specifications Processor Socket 370 BGA (mobile) or FC-PGA based Intel Pentium III or Celeron Pentium III Up to 1000MHz (100MHz PSB, 256kByte L2 cache) Mobile PIII Up to 700MHz BGA2 package with interposer (100MHz PSB, 256kByte L2 cache) Mobile Celeron BGA2 package with interposer (100Mz PSB, 128kByte L2 cache) L2 Cache 128/256kByte L2 cache depending on processor Memory 128MByte soldered synchronous DRAM with optional BIOS activated ECC feature. Additional Piggybac
ページ15に含まれる内容の要旨
ICP-PIII Product Overview 1 PCI/PCI Intel 21150 transparent bridge (Master) or Intel 21554 non-transpar- ent PCI/PCI bridge for multiprocessing (Slave) operation with Basic Hot-Swap support (PICMG 2.1 R1.0), Serialized interrupts and univer- sal (3.3/5.0V) V I/O support On-Board I/O A 10/100 MBit/s Ethernet (Intel 82559) A optional 2nd independent Fast Ethernet A Up to 2x 12Mbit/s USB A Up to 2x 400Mbit/s FireWire interfaces Rear I/O Standard to all CPU variants is option ‘C’ which provides 2nd
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Product Overview ICP-PIII 1.2 Configuration Inova’s high-performance, high-density 3U PIII board supports functionality and connectivity on all three major serial networking levels like Fast Ethernet, FireWire and USB as well as most state-of- the-art fieldbus standards such as PROFIBUS, CAN, Interbus, and LON. Three CPU groups exist to cater for the needs of all aspects of CompactPCI integration: The high- end typically supports 128MBytes on-board soldered SDRAM, Lynx3DM graphic controller wit
ページ17に含まれる内容の要旨
ICP-PIII Product Overview Figure 1.20 ICP-PIII Overview 1 100/10Mbit Ethernet FireWire VGA, ) GigaST R USB FLASH Extension: PanelLink Up to 512MByte LVDS, Socket 370 or BGA2 based Intel Pentium III or Celeron TFT, ) GigaST R, PanelLink or LVDS Optional Lynx3DM or Radeon VE Graphic Controller (Under- side) North-Bridge PCI Interface for Piggyback Extensions 128MB or 384MB Optional SDRAM Extension Multiprocessing 512MByte in Development Inova’s CPUs have been prepared for rear I/O operation. Cur
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Product Overview ICP-PIII 1.3 Software 1.31 Linux Being a modern operating system, Linux executes a 32-bit architecture, uses pre-emptive multi- tasking, has protected memory, supports multiple users, and has rich support for networking, including TCP/IP. Linux was originally written for Intel’s 386 architecture, but now runs on a wide variety of hardware platforms including the full x86 family of processors as well as Alpha, SPARC, and PowerPC. Linux’s architecture also creates a more reliable
ページ19に含まれる内容の要旨
ICP-PIII Product Overview 1.34 Windows CE Microsoft® Windows CE is an operating system designed for a wide variety of embedded systems 1 and products, from hand-held PCs and consumer electronic devices to specialized industrial con- trollers and embedded communications devices. The Windows CE operating system has proved itself capable of handling the most demanding 32-bit embedded applications by bringing the full power of the Microsoft's 32-bit programming and operating systems technology to th
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Product Overview ICP-PIII 1.4 Hardware 1.41 Block Diagram Figure 1.41 Block Diagram x86 Ôprocessor Pentium III, Celeron Silicon Motion VGA Lynx3DM GigaST)R Socket or PanelLink AGP FC-PGA 370 ATI Radeon VE TFT or Graphics BGA2 (Mobile) SDRAM (ECC) 8/16 MByte 128 MByte SGRAM On-Board 10/100 Mbit/s Intel 82559 Ethernet 128/384 MByte Ethernet North Bridge Piggyback PC100 Intel 82443BX Extension 10/100 Mbit/s Intel 82559 Ethernet Ethernet PCI/PCI Bridge PCI Bus 400 Mbit/s System Slot PL TSB 12LV23 Fi
