Freescale Semiconductor MPC8260の取扱説明書

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MPC8260 PowerQUICC™ II
Family Reference Manual
Supports
MPC8250
MPC8255
MPC8260
MPC8264
MPC8265
MPC8266
MPC8260RM
Rev. 2, 12/2005

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How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) Information in this document is provided solely to enable

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Part I—Overview I Overview 1 G2 Core 2 Memory Map 3 Part II—Configuration and Reset II System Interface Unit (SIU) 4 Reset 5 Part III—The Hardware Interface III External Signals 6 60x Signals 7 The 60x Bus 8 PCI Bridge 9 Clocks and Power Control 10 Memory Controller 11 Secondary (L2) Cache Support 12 IEEE 1149.1 Test Access Port 13 Part IV—Communications Processor Module IV Communications Processor Module Overview 14 Serial Interface with Time-Slot Assigner 15 CPM Multiplexing 16 Baud-Rate Gener

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I Part I—Overview 1 Overview 2 G2 Core 3 Memory Map II Part II—Configuration and Reset 4 System Interface Unit (SIU) 5 Reset III Part III—The Hardware Interface 6 External Signals 7 60x Signals 8 The 60x Bus 9 PCI Bridge 10 Clocks and Power Control 11 Memory Controller 12 Secondary (L2) Cache Support 13 IEEE 1149.1 Test Access Port IV Part IV—Communications Processor Module 14 Communications Processor Module Overview 15 Serial Interface with Time-Slot Assigner 16 CPM Multiplexing 17 Baud-Rate Ge

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Fast Ethernet Controller 35 FCC HDLC Controller 36 FCC Transparent Controller 37 Serial Peripheral Interface (SPI) 38 2 I C Controller 39 Parallel I/O Ports 40 Register Quick Reference Guide A Reference Manual (Rev 1) Errata B Glossary of Terms and Abbreviations GLO Index IND

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35 Fast Ethernet Controller 36 FCC HDLC Controller 37 FCC Transparent Controller 38 Serial Peripheral Interface (SPI) 2 39 I C Controller 40 Parallel I/O Ports A Register Quick Reference Guide B Reference Manual (Rev 1) Errata GLO Glossary of Terms and Abbreviations IND Index

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Contents Paragraph Page Number Title Number About This Book Reference Manual Revision History............................................................................ lxxvii Before Using this Manual—Important Note ................................................................ lxxix Audience ....................................................................................................................... lxxix Organization.................................................................

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Contents Paragraph Page Number Title Number 1.7.2.5 PCI with 155-Mbps ATM ...................................................................................... 1-22 1.7.2.6 PowerQUICC II as PCI Agent............................................................................... 1-23 Chapter 2 G2 Core 2.1 Overview.......................................................................................................................... 2-1 2.2 G2 Processor Core Features .........................

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Contents Paragraph Page Number Title Number 2.5.1 PowerPC Exception Model........................................................................................ 2-21 2.5.2 PowerQUICC II Implementation-Specific Exception Model.................................... 2-22 2.5.3 Exception Priorities.................................................................................................... 2-25 2.6 Memory Management...............................................................................

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Contents Paragraph Page Number Title Number 4.3.1.7 SIU External Interrupt Control Register (SIEXR)................................................. 4-25 4.3.2 System Configuration and Protection Registers ........................................................ 4-26 4.3.2.1 Bus Configuration Register (BCR)........................................................................ 4-26 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)........................................... 4-29 4.3.2.3 6

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Contents Paragraph Page Number Title Number 5.4.2.2 Single PowerQUICC II Configured from Boot EPROM ...................................... 5-10 5.4.2.3 Multiple PowerQUICC IIs Configured from Boot EPROM ................................. 5-11 5.4.2.4 Multiple PowerQUICC IIs in a System with No EPROM .................................... 5-13 Chapter 6 External Signals 6.1 Functional Pinout............................................................................................................

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Contents Paragraph Page Number Title Number 7.2.4.4.2 Global (GBL)—Input .......................................................................................... 7-8 7.2.4.5 Caching-Inhibited (CI)—Output ............................................................................. 7-8 7.2.4.6 Write-Through (WT)—Output ................................................................................ 7-9 7.2.5 Address Transfer Termination Signals...................................................

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Contents Paragraph Page Number Title Number 8.2.2 60x-Compatible Bus Mode.......................................................................................... 8-3 8.3 60x Bus Protocol Overview............................................................................................. 8-4 8.3.1 Arbitration Phase ......................................................................................................... 8-5 8.3.2 Address Pipelining and Split-Bus Transactions....................

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Contents Paragraph Page Number Title Number 9.6 60x Bus Arbitration Priority ............................................................................................ 9-4 9.7 60x Bus Masters............................................................................................................... 9-4 9.8 CompactPCI Hot Swap Specification Support ................................................................ 9-5 9.9 PCI Interface ..........................................................

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Contents Paragraph Page Number Title Number 9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx) ..................................... 9-31 9.11.1.6 Discard Timer Control Register (PTCR) .............................................................. 9-32 9.11.1.7 General Purpose Control Register (GPCR) .......................................................... 9-33 9.11.1.8 PCI General Control Register (PCI_GCR) ........................................................... 9-35 9.11.1.9 Error

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Contents Paragraph Page Number Title Number 9.11.2.27 PCI Configuration Register Access in Big-Endian Mode .................................... 9-62 9.11.2.27.1 Additional Information on Endianess ............................................................... 9-63 9.11.2.27.2 Notes on GPCR[LE_MODE] ........................................................................... 9-63 9.11.2.28 Initializing the PCI Configuration Registers ........................................................ 9-64 9

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Contents Paragraph Page Number Title Number 9.13.1.6.2 DMA Status Register [0–3] (DMASRx) .......................................................... 9-90 9.13.1.6.3 DMA Current Descriptor Address Register [0–3] (DMACDARx) .................. 9-91 9.13.1.6.4 DMA Source Address Register [0–3] (DMASARx) ........................................ 9-92 9.13.1.6.5 DMA Destination Address Register [0–3] (DMADARx) ................................ 9-92 9.13.1.6.6 DMA Byte Count Register [0–3] (DMABCRx) ....

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Contents Paragraph Page Number Title Number 10.6 PowerQUICC II Internal Clock Signals ........................................................................ 10-5 10.6.1 General System Clocks.............................................................................................. 10-5 10.7 PLL Pins ........................................................................................................................ 10-6 10.8 System Clock Control Register (SCCR)...........................

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Contents Paragraph Page Number Title Number 11.4 SDRAM Machine ........................................................................................................ 11-33 11.4.1 Supported SDRAM Configurations......................................................................... 11-35 11.4.2 SDRAM Power-On Initialization ............................................................................ 11-35 11.4.3 JEDEC-Standard SDRAM Interface Commands ..........................................

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Contents Paragraph Page Number Title Number 11.6.1.4 Exception Requests.............................................................................................. 11-67 11.6.2 Programming the UPMs .......................................................................................... 11-67 11.6.3 Clock Timing ........................................................................................................... 11-67 11.6.4 The RAM Array.................................................