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CM71-10106-1E
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR30
32-Bit Microcontroller
MB91F109
Hardware Manual
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FR30 32-Bit Microcontroller MB91F109 Hardware Manual FUJITSU LIMITED
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PREFACE ■ Objectives and Intended Reader The MB91F109 has been developed as one of the "32-bit single-chip microcontroller FR30 series" products that use new RISC architecture CPUs as their cores. It has optimal specifications for embedding applications that require high CPU processing power. This manual explains the functions and operations of the MB91F109 for the engineers who actually develop products using the MB91F109. Read this manual thoroughly. Refer to the instruction manual for deta
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■ Organization of This Manual This manual consists of 16 chapters and an appendix. Chapter 1 Overview Chapter 1 provides basic general information on the MB91F109, including its characteristics, a block diagram, and function overview. Chapter 2 CPU Chapter 2 provides basic information on the FR series CPU core functions including the architecture, specifications, and instructions. Chapter 3 Clock Generator and Controller Chapter 3 provides detailed information on the generation and control
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Chapter 14 PWM Timer Chapter 14 provides an overview of the PWM timer, explains the register configuration and functions, and operations of the PWM timer. Chapter 15 DMAC Chapter 15 provides an overview of the DMAC, explains the register configuration and functions, and operations of the DMAC. Chapter 16 Flash Memory Chapter 16 explains the flash memory functions and operations. The chapter provides information on using the flash memory from the FR CPU. For information on using the flash memo
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1. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this inf
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How to Read This Manual ■ Description Format of this Manual Major terms used in this manual are explained below: Term Meaning I-BUS 16-bit wide bus used for internal instructions. Since the FR series uses an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-BUS. D-BUS Internal 32-bit wide data bus. Internal resources are connected to the D-BUS. C-BUS Internal multiplex bus. The C-BUS is connected to the I-BUS and D-
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CONTENTS CHAPTER 1 OVERVIEW ................................................................................................... 1 1.1 MB91F109 Characteristics .................................................................................................................... 2 1.2 General Block Diagram of MB91F109 ................................................................................................... 6 1.3 Outside Dimensions ...........................................................
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3.9 Gear Function ..................................................................................................................................... 87 3.10 Standby Mode (Low Power Consumption Mechanism) ...................................................................... 90 3.10.1 Stop State ...................................................................................................................................... 92 3.10.2 Sleep State .........................................
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4.17.17 Hyper DRAM Interface: Read ....................................................................................................... 188 4.17.18 Hyper DRAM Interface: Write ....................................................................................................... 189 4.17.19 Hyper DRAM Interface ................................................................................................................. 190 4.17.20 DRAM Refresh .............................................
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10.5 Serial Status Register (SSR) ............................................................................................................ 253 10.6 UART Operation ............................................................................................................................... 255 10.7 Asynchronous (Start-Stop) Mode ...................................................................................................... 257 10.8 CLK Synchronous Mode .............................
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15.5 Descriptor Register in RAM ............................................................................................................... 332 15.6 DMAC Transfer Modes ...................................................................................................................... 335 15.7 Output of Transfer Request Acknowledgment and Transfer End signals .......................................... 338 15.8 Notes on DMAC ..................................................................
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FIGURES Figure 1.2-1 General Block Diagram of MB91F109 ........................................................................................ 6 Figure 1.3-1 Outside Dimensions of FPT-100P-M06 ...................................................................................... 7 Figure 1.3-2 Outside Dimensions of FPT-100P-M05 ...................................................................................... 8 Figure 1.3-3 Outside Dimensions of BGA-112P-M01 .............................
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Figure 3.15-1 Example of PLL Clock Setting ................................................................................................. 108 Figure 3.15-2 Clock System Reference Diagram .......................................................................................... 109 Figure 4.1-1 Bus Interface Registers ........................................................................................................... 113 Figure 4.1-2 Bus Interface Block Diagram .........................
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Figure 4.17-12 Example 5 of Write Cycle Timing Chart .................................................................................. 169 Figure 4.17-13 Example of Read and Write Combination Cycle Timing Chart ............................................... 170 Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart ..................................................................... 171 Figure 4.17-15 Example of External Wait Cycle Timing Chart ........................................
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Figure 7.1-1 Delayed Interrupt Module Register .......................................................................................... 220 Figure 7.1-2 Delayed Interrupt Module Block Diagram ................................................................................ 220 Figure 8.1-1 Interrupt Controller Registers (1/2) .......................................................................................... 225 Figure 8.1-2 Interrupt Controller Registers (2/2) ..........................
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Figure 14.10-1 One-Shot Operation Timing Chart (Trigger Restart Disabled) ................................................ 318 Figure 14.10-2 One-Shot Operation Timing Chart (Trigger Restart Enabled) ................................................ 318 Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal Polarity) ................................ 319 Figure 14.12-1 Example of Keeping PWM Output at a Lower Level .............................................................
