ページ1に含まれる内容の要旨
56F8322/56F8122
Data Sheet
Preliminary Technical Data
56F8300
16-bit Hybrid Controllers
MC56F8322
Rev. 10.0
10/2004
freescale.com
ページ2に含まれる内容の要旨
Document Revision History Version History Description of Change Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues Rev 4.0 Added Package Pins to GPIO table in Section 8. Clarification of TRST usage in this device. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in
ページ3に含まれる内容の要旨
56F8322/56F8122 General Description Note: Features in italics are NOT available in the 56F8122 device. • Up to 60 MIPS at 60MHz core frequency • FlexCAN module • DSP and MCU functionality in a unified, • Up to two Serial Communication Interfaces (SCIs) C-efficient architecture • Up to two Serial Peripheral Interfaces (SPIs) • 32KB Program Flash • Two general-purpose Quad Timers • 4KB Program RAM • Computer Operating Properly (COP)/Watchdog • 8KB Data Flash • On-Chip Relaxation Oscillator • 8KB
ページ4に含まれる内容の要旨
Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5 Part 8: General Purpose Input/Output 1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 5 (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96 1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96 1.3. Award-Winning Development Environment . 8 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96 1.4. A
ページ5に含まれる内容の要旨
56F8322/56F8122 Features Part 1 Overview 1.1 56F8322/56F8122 Features 1.1.1 Hybrid Controller Core • Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture • Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Four 36-bit accumulators, including extension bits • Arithmetic and logic multi-bit shifter • Parallel instruction set with unique DSP addressing modes • Hardware DO an
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1.1.3 Memory Note: Features in italics are NOT available in the 56F8122 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection • On-chip memory, including a low-cost, high-volume Flash solution — 32KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 8KB of Data RAM — 8KB of Boot Flash • EEPROM emulation capability 1.1.4 Peripheral Circuits Note: Features in italics are NOT available in the 56F8122 device. •
ページ7に含まれる内容の要旨
Device Description 1.1.5 Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available • ADC smart power management • Each peripheral can be individually disabled to save power 1.2 Device Description The 56F8322 and 56F8122 are members of the 56800E core
ページ8に含まれる内容の要旨
is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to direct
ページ9に含まれる内容の要旨
Architecture Block Diagram 1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures. The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and c
ページ10に含まれる内容の要旨
4 JTAG / EOnCE Boot Flash pdb_m[15:0] Program pab[20:0] Flash Program cdbw[31:0] RAM 56800E CHIP TAP Controller TAP Linking Data RAM xab1[23:0] Module xab2[23:0] Data External Flash JTAG Port cdbr_m[31:0] xdb2_m[15:0] To Flash Control Logic IPBus Bridge Flash Not available on the 56F8122 device. Memory Module IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory Module (FM). Flash control is accomplished by the I/O to the FM over the perip
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Architecture Block Diagram To/From IPBus Bridge CLKGEN Interrupt (OSC/PLL) Controller (ROSC) Low-Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM COP Reset 2 FlexCAN COP 4 2 SPI 1 SCI 1 4 SPI 0 PWMA 3 SYNC Output GPIO A 2 SCI 0 GPIO B GPIO C ch2i 2 Timer C ch2o 6 ADCA TEMP_SENSE The dotted line on Temperature Sense signifies the Not available on the 56F8122 device. pad-to-pad bond between TEMP_SENSE and ANA7 on the 56F8322 IPBus Figure 1-2 Peripheral Subsystem
ページ12に含まれる内容の要旨
Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus. cdbw[31:0] Primary core data
ページ13に含まれる内容の要旨
Product Documentation 1.5 Product Documentation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8322 and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com/semiconductors/. Table 1-3 Chip Documentation Topic Description Order Number DSP56800E Detailed description of the 56800E family architect
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Number of Pins in Package Functional Group 56F8322 56F8122 Power (V or V ) 55 DD DDA Ground (V or V ) 55 SS SSA 1 22 Supply Capacitors & V PP
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Introduction PHASEA0 (TA0, GPIOB7) V DD_IO 1 Power Quadrature 4 PHASEB0 (TA1, GPIOB6) V Decoder 0 SS Ground 1 4 or Quad V INDEX0 (TA2, GPIOB5) DDA_ADC Timer A or Power 1 1 GPIO V SSA_ADC HOME0 (TA3, GPIOB4) Ground 1 1 56F8322 SCLK0 (GPIOB3) 1 Other V 1 - V 2 CAP CAP 2 Supply MOSI0 (GPIOB2) SPI0 or 1 Ports SCI1 or MISO0 (RXD1, GPIOB1) GPIO 1 EXTAL (GPIOC0) SS0 (TXD1, GPIOB0) PLL and 1 1 Clock or XTAL (GPIOC1) GPIO 1 PWMA0 -1 (GPIOA0 - 1) 2 PWMA2 (SS1, GPIOA2) 1 PWMA3 (MISO1, GPIOA3) PWMA or
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TA0 (GPIOB7) V DD_IO 1 Power 4 TA1 (GPIOB6) V Quad SS 1 Ground 4 Timer A or V TA2 (GPIOB5) DDA_ADC Power GPIO 1 1 V SSA_ADC TA3 (GPIOB4) Ground 1 1 56F8122 SCLK0 (GPIOB3) 1 Other V 1 - V 2 CAP CAP 2 Supply MOSI0 (GPIOB2) SPI0 or 1 Ports SCI1 or MISO0 (RXD1, GPIOB1) GPIO 1 EXTAL (GPIOC0) SS0 (TXD1, GPIOB0) PLL and 1 1 Clock or XTAL (GPIOC1) GPIO 1 GPIOA0 - 1 2 SS1 (GPIOA2) 1 MISO1 (GPIOA3) SPI1 or 1 GPIO MOSI1 (GPIOA4) 1 SCLK1 (GPIOA5) 1 GPIOA6 1 ANA0 - 2 3 ANA4 - 6 ADCA 3 V REF 3 GPIOC2 1
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Signal Pins 2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). In the 56F8122, after reset, each pin must be configured for the desired function. The initialization software will configure each pin for the function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed. Note: Signals in italics are not available in the 56F8122 device. If the “State During Reset” lists more than one state for a pin, the first st
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Table 2-2 Signal and Package Information for the 48-Pin LQFP State During Signal Name Pin No. Type Signal Description Reset EXTAL 32 Input/ Input External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to V . SS The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. (GPIOC0) Sc
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Signal Pins Table 2-2 Signal and Package Information for the 48-Pin LQFP State During Signal Name Pin No. Type Signal Description Reset PHASEA0 38 Schmitt Input Phase A — Quadrature Decoder 0, PHASEA input Input (TA0) Schmitt Input TA0 — Timer A, Channel 0 Input/ Output (GPIOB7) Schmitt Input Port B GPIO — This GPIO pin can be individually programmed as an Input/ input or output pin. Output (oscillator_ Output Output Clock Output - can be used to monitor the internal oscillator clock clock)
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Table 2-2 Signal and Package Information for the 48-Pin LQFP State During Signal Name Pin No. Type Signal Description Reset INDEX0 36 Schmitt Input Index — Quadrature Decoder 0, INDEX input Input (TA2) Schmitt Input TA2 — Timer A, Channel 2 Input/ Output (GPIOB5) Schmitt Input Port B GPIO — This GPIO pin can be individually programmed as an Input/ input or output pin. Output (SYS_CLK) Output Output Clock Output - can be used to monitor the internal SYS_CLK signal (see Section 6.5.7 CLKO Sel
