ページ1に含まれる内容の要旨
MC68HC908MR32
MC68HC908MR16
Data Sheet
M68HC08
Microcontrollers
MC68HC908MR32
Rev. 6.1
07/2005
freescale.com
ページ2に含まれる内容の要旨
ページ3に含まれる内容の要旨
MC68HC908MR32 MC68HC908MR16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserve
ページ4に含まれる内容の要旨
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Revision Page Date Description Level Number(s) Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect 29 Register (FLBPR) at address location $FF7E August, 3.0 2001 Figure A-1. MC68HC908MR16 Memory Map — Added FLASH Block Protect 306 Register (FLBPR) at address location $F
ページ5に含まれる内容の要旨
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ6に含まれる内容の要旨
List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev. 6.1 6 Freescale Semiconductor
ページ7に含まれる内容の要旨
Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 Pin Assignm
ページ8に含まれる内容の要旨
Table of Contents 2.8.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.8.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2
ページ9に含まれる内容の要旨
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . .
ページ10に含まれる内容の要旨
Table of Contents Chapter 7 Central Processor Unit (CPU) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ページ11に含まれる内容の要旨
Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.2.2 Data Direc
ページ12に含まれる内容の要旨
Table of Contents 12.6.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.6.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.7 Initialization and the PWMEN Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.8 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . .
ページ13に含まれる内容の要旨
13.7.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.7.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.7.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.7.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ14に含まれる内容の要旨
Table of Contents 15.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 15.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ15に含まれる内容の要旨
Chapter 17 Timer Interface B (TIMB) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3.1 TIMB Counter Pres
ページ16に含まれる内容の要旨
Table of Contents 18.3 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 18.3.1.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 18.3.1.2 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . .
ページ17に含まれる内容の要旨
Chapter 1 General Description 1.1 Introduction The MC68HC908MR32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908MR16 with the exceptions shown in Appendix A MC68HC908MR16. 1.2 Features Features include: H
ページ18に含まれる内容の要旨
General Description Available packages: – 64-pin plastic quad flat pack (QFP) – 56-pin shrink dual in-line package (SDIP) Low-power design, fully static with wait mode Master reset pin (RST) and power-on reset (POR) Stop mode as an option Break module (BRK) supports setting the in-circuit simulator (ICS) single break point Features of the CPU08 include: Enhanced M68HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the M68HC05) 16-bit
ページ19に含まれる内容の要旨
MCU Block Diagram MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 19 INTERNAL BUS M68HC08 CPU PTA7–PTA0 CPU ARITHMETIC/LOGIC REGISTERS UNIT LOW-VOLTAGE INHIBIT MODULE PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 COMPUTER OPERATING PROPERLY CONTROL AND STATUS REGISTERS — 112 BYTES PTB4/ATD4 MODULE PTB3/ATD3 PTB2/ATD2 USER FLASH — 32,256 BYTES TIMER INTERFACE PTB1/ATD1 MODULE A PTB0/ATD0 USER RAM — 768 BYTES PTC6 PTC5 TIMER INTERFACE MODULE B PTC4 MONITOR ROM — 240 BYTES PTC3 PTC2 (1)
ページ20に含まれる内容の要旨
General Description 1.4 Pin Assignments Figure 1-2 shows the 64-pin QFP pin assignments and Figure 1-3 shows the 56-pin SDIP pin assignments. PTB2/ATD2 IRQ 1 48 PTB3/ATD3 PTF5/TxD 2 47 PTB4/ATD4 PTF4/RxD 3 46 PTB5/ATD5 PTF3/MISO 4 45 PTB6/ATD6 PTF2/MOSI 5 44 PTB7/ATD7 PTF1/SS 6 43 PTC0/ATD8 PTF0/SPSCK 7 42 V PTC1/ATD9 SS 8 41 V V 9 40 DDAD DD V PTE7/TCH3A 10 39 SSAD V PTE6/TCH2A 11 38 REFL V PTE5/TCH1A 12 37 REFH PTC2 PTE4/TCH0A 13 36 PTC3 PTE3/TCLKA 14 35 PTC4 PTE2/TCH1B 15 34 PTC5 PTE1/TCH0B
