ページ1に含まれる内容の要旨
NS9215
Hardware Reference
90000847_C
Release date: 10 April 2008
ページ2に含まれる内容の要旨
©2008 Digi International Inc. Printed in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, a Digi International Company, ConnectCore, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners. Information in this document is subject to change without notice and does not represent a commitment on the
ページ3に含まれる内容の要旨
ページ4に含まれる内容の要旨
ページ5に含まれる内容の要旨
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Pinout (265) ..................................................... 27 The Legend .............................................................................. 27 Memory bus interface......................................................................... 28 Ethernet interface MAC...........................................................
ページ6に含まれる内容の要旨
GPIO Configuration Register #15 ..................................................... 63 GPIO Configuration Register #16 ..................................................... 64 GPIO Configuration Register #17 ..................................................... 64 GPIO Configuration Register #18 ..................................................... 65 GPIO Configuration Register #19 ..................................................... 65 GPIO Configuration Register #20 .......................
ページ7に含まれる内容の要旨
ICache and DCache behavior ..........................................................90 R2: Translation Table Base register.........................................................91 Register format..........................................................................91 R3:Domain Access Control register..........................................................91 Register format..........................................................................91 Access permissions and instructions ...
ページ8に含まれる内容の要旨
Access instructions ....................................................................103 Register format ........................................................................103 Performing a fast context switch ...................................................103 Context ID register ....................................................................104 Access instructions ....................................................................104 Register format ............................
ページ9に含まれる内容の要旨
MMU faults and CPU aborts................................................................. 119 Alignment fault checking ............................................................ 119 Fault Address and Fault Status registers .......................................... 119 Priority encoding table............................................................... 120 Fault Address register (FAR)......................................................... 120 FAR values for multi-word transfers ..........
ページ10に含まれる内容の要旨
High speed bus system................................................................138 High-speed bus arbiters...............................................................138 How the bus arbiter works ...........................................................138 Ownership...............................................................................139 Locked bus sequence..................................................................139 Relinquishing the bus .............................
ページ11に含まれる内容の要旨
AHB Error Detect Status 2 .................................................................. 160 AHB Error Monitoring Configuration register ............................................ 161 Timer Master Control register ............................................................. 162 Timer 0–4 Control registers................................................................. 164 Timer 5 Control register .................................................................... 166 Timer 6–9 Control r
ページ12に含まれる内容の要旨
Low-power SDRAM partial array refresh ...........................................204 Memory map...................................................................................205 Power-on reset memory map ........................................................205 Chip select 1 memory configuration................................................205 Example: Boot from flash, SRAM mapped after boot ............................205 Example: Boot from flash, SDRAM remapped after boot .............
ページ13に含まれる内容の要旨
222 Memory banks constructed from 16-or 32-bit memory devices................ 223 Dynamic memory controller................................................................ 225 Write protection ...................................................................... 225 Access sequencing and memory width............................................. 225 SDRAM Initialization ......................................................................... 225 Left-shift value table: 32-bit wide data bus SDRA
ページ14に含まれる内容の要旨
Static Memory Write Delay 0–3 registers..................................................257 StaticMemory Turn Round Delay 0–3 registers ...........................................258 Chapter 6: Ethernet Communication Module ...................... 261 Features.................................................................................261 Common acronyms ....................................................................261 Ethernet communications module ....................................
ページ15に含まれる内容の要旨
Writing to other registers............................................................ 276 Ethernet Control and Status registers .................................................... 277 Register address filter................................................................ 277 Ethernet General Control Register #1 .................................................... 279 Ethernet General Control Register #2 .................................................... 282 Ethernet General Status register .
ページ16に含まれる内容の要旨
Transmit statistics counters address map .........................................307 Transmit byte counter (A060 06E0).................................................307 Transmit packet counter (A060 06E4) ..............................................308 Transmit multicast packet counter (A060 06E8)..................................308 Transmit broadcast packet counter (A060 06EC) .................................308 Transmit deferral packet counter (A060 06F4) ...............................
ページ17に含まれる内容の要旨
Multicast Low Address Filter Register #6.......................................... 328 Multicast Low Address Filter Register #7.......................................... 328 Multicast High Address Filter Register #0 ......................................... 328 Multicast High Address Filter Register #1 ......................................... 328 Multicast High Address Filter Register #2 ......................................... 328 Multicast High Address Filter Register #3 ....................
ページ18に含まれる内容の要旨
Buffer length ...........................................................................340 Destination address [pointer]........................................................340 Status....................................................................................341 Wrap (W) bit............................................................................341 Interrupt (I) bit.........................................................................341 Last (L) bit .........................
ページ19に含まれる内容の要旨
Last (L) bit ............................................................................. 358 Full (F) bit.............................................................................. 358 Decryption .................................................................................... 359 ECB processing ............................................................................... 359 Processing flow diagram ............................................................. 359 CBC, CFB, OFB, and CT
ページ20に含まれる内容の要旨
[Module] DMA RX Control....................................................................375 [Module] DMA RX Buffer Descriptor Pointer ..............................................376 [Module] RX Interrupt Configuration register ............................................377 [Module] Direct Mode RX Status FIFO......................................................378 [Module] Direct Mode RX Data FIFO .......................................................379 [Module] DMA TX Control...........
