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NS9210 Processor Module
Hardware Reference
90001002_A
August 2008
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©2008 Digi International Inc. All rights reserved. Digi, Digi International, the Digi logo, a Digi International Company, Digi JumpStart Kit, ConnectCore, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners.
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer support .............................................................................. 7 Chapter 1: About the Module .............................. 9 Features and functionality ............................................................10 Module variant ................................................................................10 M
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GPIO multiplex table .........................................................................28 External interrupts ............................................................................32 Interfaces ................................................................................33 10/100 Mbps Ethernet port ..................................................................33 UART ............................................................................................33 SPI ...........
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LEDs ...................................................................................... 44 WLAN LED LE7 ................................................................................. 44 Power LEDs, LE3 and LE4 .................................................................... 44 User LEDs, LE5 and LE6 ...................................................................... 44 Serial status LEDs ............................................................................. 45 Status LEDs Se
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Power Jack, X24 ...............................................................................58 Ethernet interface .....................................................................58 RJ-45 pin allocation, X19 ....................................................................59 LEDs .............................................................................................60 Peripheral (expansion) headers ......................................................60 Peripheral application he
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This guide provides information about the Digi NS9210 Processor Module embedded core module. Conventions used This table describes the typographic conventions used in this guide: in this guide This convention Is used for italic type Emphasis, new terms, variables, and document titles. monospaced type Filenames, pathnames, and code examples. Digi information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8 ConnectCore 9P 9215 Hardware Reference
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About the Module CHA P T E R 1 The NS9210 Processor Module is part of the ConnectCore embedded core processor module family. Built on leading Digi technology, the network-enabled ConnectCore 9P family provides a modular and scalable core processor solution that significantly minimizes hardware and software design risk. This module combines superior performance and a complete set of integrated peripherals and component connectivity options in a compact and versatile form factor. The NS9210 P
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Chapter 1 Features and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit NET+ARM (ARM926EJ-S) RISC processor NS9215 @ 150MHz ARM9 core with memory management unit (MMU) 4K data cache/4K instruction cache 8MB SDRAM (can support a maximum of 64MB SDRAM) 4MB NOR Flash (can support a maximum of 16MB NOR flash) 10 general purpose timers; NS9210 Processor Module
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Pinout legend: Type I Input O Output I/O Input or output PPower X1 pinout X1 pin Type Module functionality Usage on Comments number Development board 1 P GND GND 2 P GND GND 3 I RSTIN# RSTIN# 10k pull-up on module 4 O PWRGOOD PWRGOOD Output of the reset controller push pull with 470R current limiting resistor 5 O RSTOUT# RSTOUT# Output of logical AND function between NS9215 RESET_DONE and NS9215 RESET_OUT# 6 I TCK TCK JTAG - 10k pull-up on module 7 I TMS TMS JTAG - 10k pull-up on module 8 I
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Chapter 1 X1 pin Type Module functionality Usage on Comments number Development board 20 P GND GND 21 I/O D0 D0 Buffered Data - only active when either CS0# or CS2# is active NS9215 D[31:16] 22 I/O D1 D1 23 I/O D2 D2 24 I/O D3 D3 25 I/O D4 D4 26 I/O D5 D5 27 I/O D6 D6 28 I/O D7 D7 29 I/O D8 D8 30 I/O D9 D9 31 I/O D10 D10 32 I/O D11 D11 33 I/O D12 D12 34 I/O D13 D13 35 I/O D14 D14 36 I/O D15 D15 37 P GND GND 38 O AO AO Buffered Address always active 39 O A1 A1 40 O A2 A2 41 O A3 A3 42 O A4 A4
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X1 pin Type Module functionality Usage on Comments number Development board 51 O A13 A13 52 O A14 A14 53 O A15 A15 54 O A16 A16 55 O GND GND 56 O EXT_OE# EXT_OE# 57 O EXT_WE# EXT_WE# 58 O CSO# CSO# 59 O CS2# CS2# 60 O BLE# BLE# NS9215 BE2# 61 O BHE# BHE# NS9215 BE3# 62 I EXT_WAIT# EXT_WAIT# 10k pull-up on module 63 O BCLK BCLK Connected over a 22R resistor to NS9215 CLK_OUT1 pin 64 P GND GND 65 I ETH_TPIN ETH_TPIN 66 O ETH_ACTIVITY# ETH_ACTIVITY# Low active signal with 330R resistor on module
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Chapter 1 X1 pin Type Module functionality Usage on Comments number Development board 78 P VRTC VRTC Backup Battery for RTC, for 3V cell. Can be left floating, if RTC backup not needed. 79 P VLIO VLIO Mobile: Power from Li-Ion Battery (2.5V-5.5V) Non-Mobile: connected to 3.3V 80 P GND GND 14 NS9210 Processor Module Hardware Reference
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X2 pinout X2 pin Type Module functionality Usage on Comments number Development board 1 P GND 2 P GND 3 I/O DCDA#/ DMA0_DONE/ PIC_0_GEN_IO[0] GPIO0/ SPI_EN (dup) 4I/O CTSA#/ EIRQ0/ PIC_0_GEN_IO[1] GPIO1/ -reserved- 5I/O DSRA#/ EIRQ1/ PIC_0_GEN_IO[2] GPIO2/ -reserved- 6 I/O RXDA/ DMA0_PDEN/ PIC_0_GEN_IO[3] GPIO3/ SPI_RX (dup) 7I/O RIA#/ EIRQ2/ Timer6_in/ GPIO4 SPI_CLK (dup)/ 8 I/O RTSA#/ RS485CTLA EIRQ3/ Timer6_Out/ GPIO5/ SPI_CLK (dup)/ 9 I/O DTRA#/ TXCLKA DMA0_REQ/ Timer7_In/ GPIO6/ PIC_DBG_DAT
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Chapter 1 X2 pin Type Module functionality Usage on Comments number Development board 10 I/O TXDA/ Timer8_In/ Timer7_Out/ GPIO7/ SPI_TX (dup) 11 I/O DCDC#/ DMA1_DONE/ Timer8_Out/ GPIO8/ SPIB_EN (dup)/ 12 I/O CTSC#/ I2C_SCK/ EIRQ0 (dup)/ GPIO9/ PIC_DBG_DATA_IN 13 I/O DSRC#/ QDCI/ EIRQ1 (dup) GPIO10/ PIC_DBG_CLK 14 I/O RXDC/ DMA1_DP/ EIRQ2 (dup)/ GPIO11/ SPI_RXboot 15 I/O RIC#/ RXCLKC When booting, NS9215 RIC# signal is default configured as I2C_SDA/ Output, RST_DONE. To avoid RST_DONE/ input/o
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X2 pin Type Module functionality Usage on Comments number Development board 18 I/O TXDC/ Timer9_In/ PIC_0_CAN_TXD GPIO15/ SPI_ENboot 19 I/O DCDB# (dup)/ PIC_0_BUS_1[8] PIC_1_BUS_1[8] GPIO51/ 20 I/O CTSB# (dup)/ PIC_0_BUS_1[9] PIC_1_BUS_1[9] GPIO52/ 21 I/O DSRB# (dup)/ PIC_0_BUS_1[10] PIC_1_BUS_1[10] GPIO53/ 22 I/O RXDB (dup)/ PIC_0_BUS_1[11] PIC_1_BUS_1[11] GPIO54/ 23 I/O RIB# (dup)/ PIC_0_BUS_1[12] PIC_1_BUS_1[12] GPIO55/ 24 I/O RTSB# (dup) / RS485CTLB (dup) / PIC_0_BUS_1[13] PIC_1_BUS_1[13] GP
ページ18に含まれる内容の要旨
Chapter 1 X2 pin Type Module functionality Usage on Comments number Development board 27 I/O DCDD# (dup) / PIC_0_BUS_1[16] PIC_1_BUS_1[16] GPIO59/ 28 I/O CTSD# (dup)/ PIC_0_BUS_1[17] PIC_1_BUS_1[17] GPIO60/ 29 I/O DSRD# (dup)/ PIC_0_BUS_1[18] PIC_1_BUS_1[18] GPIO61/ 30 I/O RXDD (dup)/ PIC_0_BUS_1[19] PIC_1_BUS_1[19] GPIO62/ 31 I/O RID# (dup)/ PIC_0_BUS_1[20] PIC_1_BUS_1[20] GPIO63/ 32 I/O RTSD# (dup) / RS485CTLD(dup) / PIC_0_BUS_1[21] PIC_1_BUS_1[21] GPIO64/ 33 I/O TXCLKD (dup) / DTRD# (dup) / P
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X2 pin Type Module functionality Usage on Comments number Development board 37 I/O PIC_0_GEN_IO[1] PIC_1_GEN_IO[1] PIC_1_CAN_TXD GPIO69 38 I/O PIC_0_GEN_IO[2] PIC_1_GEN_IO[2] PWM0/ GPIO70 39 I/O PIC_0_GEN_IO[3] PIC_1_GEN_IO[3] PWM1/ GPIO71 40 I/O PIC_0_GEN_IO[4] PIC_1_GEN_IO[4] PWM2/ GPIO72 41 I/O PIC_0_GEN_IO[5] PIC_1_GEN_IO[5] PWM3/ GPIO73 42 I/O PIC_0_GEN_IO[6] PIC_1_GEN_IO[6] Timer0_In/ GPIO74 43 I/O PIC_0_GEN_IO[7] PIC_1_GEN_IO[7] Timer1_In/ GPIO75 44 I/O PIC_0_CTL_IO[0] PIC_1_CTL_IO[0] Tim
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Chapter 1 X2 pin Type Module functionality Usage on Comments number Development board 47 I/O PIC_0_CTL_IO[3] PIC_1_CTL_IO[3] Timer5_In/ GPIO79 48 I/O PIC_0_BUS_0[0] PIC_1_BUS_0[0] Timer6_In (dup)/ GPIO80 49 I/O PIC_0_BUS_0[1] PIC_1_BUS_0[1] Timer7_In (dup)/ GPIO81 50 I/O PIC_0_BUS_0[2] PIC_1_BUS_0[2] Timer8_In (dup)/ GPIO82 51 I/O PIC_0_BUS_0[3] PIC_1_BUS_0[3] Timer9_In (dup)/ GPIO83 52 I/O PIC_0_BUS_0[4] PIC_1_BUS_0[4] Timer0_Out/ GPIO84 53 I/O PIC_0_BUS_0[5] PIC_1_BUS_0[5] Timer1_Out/ GPIO85 5
