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NS9750 Hardware Reference
90000624_G
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NS9750 Hardware Reference Part number/version: 90000624_G Release date: March 2008 www.digiembedded.com
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©2008 Digi International Inc. Printed in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners. Information in this document is subject to change without notice and
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Contents Chapter 1: About NS9750 ............................................................................................... 1 NS9750 Features ......................................................................... 2 System-level interfaces................................................................. 8 System boot ............................................................................. 10 Reset......................................................................................
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Chapter 3: Working with the CPU ......................................................................47 About the processor.................................................................... 48 Instruction sets.......................................................................... 49 ARM instruction set.............................................................. 50 Thumb instruction set........................................................... 50 Java instruction set ...................
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TLB structure....................................................................104 Caches and write buffer..............................................................105 Cache features ..................................................................105 Write buffer .....................................................................106 Enabling the caches ............................................................107 Cache MVA and Set/Way formats .........................................
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Interrupt Status Raw ...........................................................152 Timer Interrupt Status register...............................................153 Software Watchdog Configuration register .................................153 Software Watchdog Timer register ..........................................155 Clock Configuration register ..................................................155 Reset and Sleep Control register .............................................157 Miscellaneou
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Dynamic memory controller .........................................................224 Write protection ................................................................224 Access sequencing and memory width ......................................224 Address mapping................................................................225 Registers ................................................................................264 Register map .............................................................
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Overview ................................................................................316 Ethernet MAC...........................................................................317 Station address logic (SAL) ....................................................321 Statistics module ...............................................................321 Ethernet front-end module ..........................................................323 Receive packet processor ..................................
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RX_D Buffer Descriptor Pointer register ....................................384 Ethernet Interrupt Status register ...........................................385 Ethernet Interrupt Enable register...........................................387 TX Buffer Descriptor Pointer register........................................389 Transmit Recover Buffer Descriptor Pointer register .....................389 TX Error Buffer Descriptor Pointer register.................................390 RX_A Buffer Descrip
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CardBus interrupts..............................................................465 Chapter 8: BBus Bridge ................................................................................................467 BBus bridge functions .................................................................468 Bridge control logic ...................................................................469 DMA accesses ....................................................................471 BBus control logic .....
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DMA buffer descriptor ................................................................504 DMA channel assignments ............................................................509 DMA Control and Status registers ...................................................510 DMA Buffer Descriptor Pointer................................................512 DMA Control register ...........................................................514 DMA Status/Interrupt Enable register ................................
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Flow charts .............................................................................556 Master module (normal mode, 16-bit).......................................556 Slave module (normal mode, 16-bit) ........................................557 Chapter 12: LCD Controller ....................................................................................559 LCD features............................................................................560 Programmable parameters ..................
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LCDPalette register.............................................................595 Interrupts ...............................................................................598 MBERRORINTR — Master bus error interrupt................................598 VCOMPINTR — Vertical compare interrupt..................................598 LBUINTR — Next base address update interrupt ...........................599 Chapter 13: Serial Control Module: UART ........................................... 601 Featu
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Serial port control and status registers ............................................650 Serial Channel B/A/C/D Control Register A ................................652 Serial Channel B/A/C/D Control Register B ................................655 Serial Channel B/A/C/D Status Register A..................................657 Serial Channel B/A/C/D Bit-rate register...................................660 Serial Channel B/A/C/D FIFO Data register ................................665 Chapter 15: IEEE 12
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Pin Interrupt Mask register....................................................700 Pin Interrupt Control register.................................................701 Granularity Count register ....................................................702 Forward Address register ......................................................703 Core Phase (IEEE1284) register ...............................................704 Chapter 16: USB Controller Module ...................................................
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HcHCCA register ................................................................739 HcPeriodCurrentED register...................................................740 HcControlHeadED register.....................................................741 HcControlCurrentED register..................................................742 HcBulkHeadED register ........................................................743 HcBulkCurrentED register .....................................................744 HcDoneHea
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Memory timing .........................................................................795 SDRAM burst read (16-bit).....................................................796 SDRAM burst read (16-bit), CAS latency = 3 ................................797 SDRAM burst write (16-bit) ....................................................798 SDRAM burst read (32-bit).....................................................799 SDRAM burst read (32-bit), CAS latency = 3 ................................800 SDRA
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SPI master mode 0 and 1: 2-byte transfer ..................................829 SPI master mode 2 and 3: 2-byte transfer ..................................829 SPI slave mode 0 and 1: 2-byte transfer ....................................830 SPI slave mode 2 and 3: 2-byte transfer ....................................830 IEEE 1284 timing .......................................................................831 IEEE 1284 timing example .....................................................831 USB timi
