ページ1に含まれる内容の要旨
®
CY62157EV30 MoBL
8-Mbit (512K x 16) Static RAM
reduces power consumption when addresses are not toggling.
Features
Place the device into standby mode when deselected (CE
1
• TSOP I package configurable as 512K x 16 or as 1M x 8 HIGH or CE LOW or both BHE and BLE are HIGH). The input
2
SRAM or output pins (IO through IO ) are placed in a high
0 15
impedance state when:
• High speed: 45 ns
• Deselected (CE HIGH or CE LOW)
1 2
• Wide voltage range: 2.20V–3.60V
• Outputs are disabled (OE HIGH
ページ2に含まれる内容の要旨
® CY62157EV30 MoBL Product Portfolio Power Dissipation Speed V Range (V) Operating I , (mA) CC CC (ns) Standby, I SB2 Product Range (µA) f = 1MHz f = f max [2] [2] [2] [2] Min Typ Max Typ Max Typ Max Typ Max CY62157EV30LL Ind’l/Auto-A 2.2V 3.0 3.6 45 1.8 3 18 25 2 8 Pin Configuration [3, 4, 5] The following pictures show the 44-pin TSOP II and 48-pin TSOP I pinouts. 44-Pin TSOP II 48-Pin TSOP I (512K x 16 / 1M x 8) Top View Top View A A 1 44 4 5 A15 1 48 A16 A A 2 43 3 6 A14 2 47 BYTE A
ページ3に含まれる内容の要旨
® CY62157EV30 MoBL Pin Configuration (continued) [3, 4, 5] The following picture shows the 48-ball VFBGA pinout. 48-Ball VFBGA Top View 1 5 2 3 4 6 A A CE BLE OE A 1 2 2 A 0 A IO A CE IO B BHE 8 3 4 1 0 C IO IO A A IO IO 2 9 10 5 6 1 V V IO A A D IO CC SS 11 17 7 3 V IO NC A IO V E SS CC 12 16 4 F IO IO A A IO IO 14 13 14 15 5 6 A A G IO NC WE IO 12 13 15 7 A A A A A NC H 18 8 9 10 11 Document #: 38-05445 Rev. *E Page 3 of 14 [+] Feedback
ページ4に含まれる内容の要旨
® CY62157EV30 MoBL [6, 7] DC Input Voltage ........... –0.3V to 3.9V (V + 0.3V) Maximum Ratings CC max Output Current into Outputs (LOW) ............................ 20 mA Exceeding maximum ratings may shorten the battery life of the Static Discharge Voltage .......................................... > 2001V device. User guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch up Current ..................................
ページ5に含まれる内容の要旨
® CY62157EV30 MoBL [10] Thermal Resistance Parameter Description Test Conditions BGA TSOP I TSOP II Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 72 74.88 76.88 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 8.86 8.6 13.52 °C/W JC (Junction to Case) AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms R1 ALL INPUT PULSES V V CC CC 90% 90% OUTPUT 10% 10% GND Fall Time = 1 V/ns Rise Time = 1 V/ns R2 30 pF INCLUDING Equivalent
ページ6に含まれる内容の要旨
® CY62157EV30 MoBL Switching Characteristics [13, 14] Over the Operating Range 45 ns (Ind’l/Auto-A) Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [15] t OE LOW to LOW-Z 5ns LZOE [15, 16] t OE HIGH to High-Z 18 ns HZOE [15] t CE LOW and CE HIGH to Low-Z 10 ns LZCE 1 2 [15, 16] t CE HIGH and CE LOW to High-Z 18
ページ7に含まれる内容の要旨
® CY62157EV30 MoBL Switching Waveforms [19, 20] Read Cycle No. 1 (Address Transition Controlled) Figure 3. Read Cycle No. 1 t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [20, 21] Read Cycle No. 2 (OE Controlled) Figure 4. Read Cycle No. 2 ADDRESS t RC CE 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE I t CC PU V CC 50% 50% SUPPLY I SB CURRENT Notes 19. The device is continuously selected
ページ8に含まれる内容の要旨
® CY62157EV30 MoBL Switching Waveforms (continued) [18, 22, 23] Write Cycle No. 1 (WE Controlled) Figure 5. Write Cycle No. 1 t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 24 DATA IO VALID DATA t HZOE [18, 22, 23] Write Cycle No. 2 (CE or CE Controlled) 1 2 Figure 6. Write Cycle No. 1 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 24 VALID DATA t HZOE Notes 22. Data IO is high impedance if OE = V . IH 23. If CE
ページ9に含まれる内容の要旨
® CY62157EV30 MoBL Switching Waveforms (continued) [23] Write Cycle No. 3 (WE Controlled, OE LOW) Figure 7. Write Cycle No. 3 t WC ADDRESS t SCE CE 1 CE 2 t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD DATA IO NOTE 24 VALID DATA t LZWE t HZWE [23] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) Figure 8. Write Cycle No. 4 t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD DATA IO NOTE 24 VALID DATA Document #: 38-05445 Rev. *E Page 9 of 14 [+] Feedback
ページ10に含まれる内容の要旨
® CY62157EV30 MoBL Truth Table CE CE WE OE BHE BLE Inputs/Outputs Mode Power 1 2 H X X X X X High-Z Deselect/Power Down Standby (I ) SB X L X X X X High-Z Deselect/Power Down Standby (I ) SB X X X X H H High-Z Deselect/Power Down Standby (I ) SB L H H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H H L H L Data Out (IO –IO ); Read Active (I ) 0 7 CC High-Z (IO –IO ) 8 15 L H H L L H High-Z (IO –IO ); Read Active (I ) 0 7 CC Data Out (IO –IO ) 8 15 L H H H L H High-Z Output Disabled Acti
ページ11に含まれる内容の要旨
® CY62157EV30 MoBL Package Diagrams Figure 9. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A B 0.75 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85150-*D Document #: 38-05445 Rev. *E Page 11 of 14 [+] Feedback 0.25 C 8.00±0.10 0.26 MAX. 0.55 MAX. 0.21±0.05 1.00 MAX 0.10 C 8.00±0.10 5.25 0.75 2.625
ページ12に含まれる内容の要旨
® CY62157EV30 MoBL Package Diagrams (continued) Figure 10. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 38-05445 Rev. *E Page 12 of 14 [+] Feedback
ページ13に含まれる内容の要旨
® CY62157EV30 MoBL Package Diagrams (continued) Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] 1 N 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] 0.004[0.10] 0.010[0.25] 0.008[0.21] GAUGE PLANE 51-85183-*A 0.020[0.50] 0.028[0.70] 0°-5° MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All
ページ14に含まれる内容の要旨
® CY62157EV30 MoBL Document History Page ® Document Title: CY62157EV30 MoBL , 8-Mbit (512K x 16) Static RAM Document Number: 38-05445 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 202940 See ECN AJU New Data Sheet *A 291272 See ECN SYT Converted from Advance Information to Preliminary Removed 48-TSOP I Package and the associated footnote Added footnote stating 44 TSOP II Package has only one CE on Page # 2 Changed V stabilization time in footnote #7 from 100 µs to 200 µs CC
