ページ1に含まれる内容の要旨
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
2K x 8 Dual-Port Static RAM
Features Functional Description
■ True dual-ported memory cells that enable simultaneous reads The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
of the same memory location are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
■ 2K x 8 organization
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or
ページ2に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Pinouts Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View) 7 6 5 4 3 2 1 52 51 50 49 48 47 52 51 50 49 48 47 46 45 44 43 42 41 40 A 1L OE A 8 46 R 1L OE 1 39 R A 2L A A A 9 45 0R 2L 2 38 0R A A A 3L 10 44 A 1R 3L 3 37 1R A 4L A A A 11 43 4L 4 36 2R 2R A 5L A A A 12 42 3R 5L 5 35 3R A 6L A A 13 41 A 6L 6 34 4R 4R 7C136/7C136A 7C136/7C136A A A 7L A A 5R 14 40 5R 7L 7 33 7C146 7C146 A A A 8L 15 39 A 8L 8 32 6R 6R A A A 9L A 9L 7R 16 38 7R
ページ3に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 DC Input Voltage ... .. .. .. ... .. .. .. .. ... .. .. .. ... .. .. .. .. ... .. .. .. −3.5V to +7.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage.......................................... > 2001V device. These user guidelines are not tested. (per MIL-STD-883, Method 3015) Storage Temperature . .. ... .. .. .. .. ... .. .. .. ..
ページ4に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Capacitance This parameter is guaranteed but not tested. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, V = 5.0V 15 pF IN A CC C Output Capacitance 10 pF OUT Figure 3. AC Test Loads and Waveforms 5V R1 893 Ω R1 893 Ω 5V 5V OUTPUT OUTPUT 281 Ω BUSY OR R2 R2 30 pF 5pF INT 347 Ω 347 Ω 30 pF INCLUDING INCLUDING JIG AND JIG AND BUSY Output Load SCOPE (a) SCOPE (b) (CY7C132/CY7C136 Only) Equivalent to: THÉVENIN EQ
ページ5に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics [8] Over the Operating Range (Speeds -15, -25, -30) (continued) [4] 7C132-25 7C132-30 [4] 7C136-15 7C136-25 7C136-30 7C146-15 7C142-25 7C142-30 Parameter Description Unit 7C146-25 7C146-30 Min Max Min Max Min Max [12] Write Cycle t Write Cycle Time 15 25 30 ns WC t CE LOW to Write End 12 20 25 ns SCE t Address Setup to Write End 12 20 25 ns AW t Address Hold from Write End 2 22 ns HA t Address Setup to Write Start 0 00 ns SA
ページ6に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics [8] Over the Operating Range (Speeds -35, -45, -55) 7C132-55 7C132-35 7C132-45 7C136-55 7C136-35 7C136-45 7C136A-55 7C142-35 7C142-45 Parameter Description Unit 7C142-55 7C146-35 7C146-45 7C146-55 Min Max Min Max Min Max Read Cycle t Read Cycle Time 35 45 55 ns RC [9] t Address to Data Valid 35 45 55 ns AA t Data Hold from Address Change 0 0 0 ns OHA [9] t CE LOW to Data Valid 35 45 55 ns ACE [9] t OE LOW to Data Valid 20 25
ページ7に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics [8] Over the Operating Range (Speeds -35, -45, -55) (continued) 7C132-55 7C132-35 7C132-45 7C136-55 7C136-35 7C136-45 7C136A-55 7C142-35 7C142-45 Parameter Description Unit 7C142-55 7C146-35 7C146-45 7C146-55 Min Max Min Max Min Max [16] Interrupt Timing t R/W to INTERRUPT Set Time 25 35 45 ns WINS t CE to INTERRUPT Set Time 25 35 45 ns EINS t Address to INTERRUPT Set Time 25 35 45 ns INS [13] t OE to INTERRUPT Reset Time 2
ページ8に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A) t RC ADDRESS ADDRESS MATCH R t PWE R/W R D VALID INR t PS ADDRESS MATCH ADDRESS L t BHA BUSY L t t BLA BDD DOUT VALID L t DDD t WDD [12, 20] Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) t WC ADDRESS t SCE CE t t HA AW t SA t PWE R/W t t SD HD DATA IN DATA VALID OE t HZOE HIGH IMPEDANCE D OUT Note 20. If OE is LOW du
ページ9に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) [12, 21] Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port) t WC ADDRESS t t SCE HA CE t AW t SA t PWE R/W t t SD HD DATA IN DATA VALID t t LZWE HZWE HIGH IMPEDANCE D OUT Figure 9. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L,R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE Valid First: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L Note 21. If the CE LO
ページ10に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Figure 10. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS ADDRESS MATCH ADDRESS MISMATCH L t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid First: t or t RC WC ADDRESS R ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS L t t BLA BHA BUSY L Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) CE t PWE R/W t t WB WH BUSY Document #: 38-06031 Rev.
ページ11に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) [16] Interrupt Timing Diagrams Figure 12. Left Side Sets INT R t WC ADDRESS WRITE 7FF L t t INS HA CE L t EINS R/W L t SA t WINS INT R Figure 13. Right Side Clears INT R t RC ADDRESS READ 7FF R t t HA INR CE R t EINR R/W R OE R t OINR INT R Figure 14. Right Side Sets INT L t WC ADDRESS WRITE 7FE R t t INS HA CE R t EINS R/W R t SA t WINS INT L Figure 15. Right Side Clears INT L t RC ADDRESS READ 7FE L t t HA INR CE
ページ12に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Figure 16. Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 120 1.4 1.2 I CC 1.2 1.0 100 I CC 1.0 0.8 80 0.8 0.6 60 V = 5.0V CC V = 5.0V CC 0.6 T = 25°C V = 5.0V A IN 0.4 40 0.4 0.2 20 I I 0.2 SB3 SB3 0 0.6 0.0 –55 25 125 0 1.0 2.0 3.0 4.0 4.0 4.5 5.0 5.5 6.0 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) NORMAL
ページ13に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 15 CY7C136-15JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial CY7C136-15NC 51-85042 52-Pin Plastic Quad Flatpack 25 CY7C136-25JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial CY7C136-25JXC 52-Pin Plastic Leaded Chip Carrier (Pb-Free) CY7C136-25NC 51-85042 52-Pin Plastic Quad Flatpack CY7C136-25NXC 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C136
ページ14に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Package Diagrams Figure 17. 52-Pin Plastic Leaded Chip Carrier, 51-85004 51-85004-*A Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042 51-85042-** Document #: 38-06031 Rev. *E Page 14 of 15 [+] Feedback
ページ15に含まれる内容の要旨
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document History Page Document Title: CY7C132, CY7C136, CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Document Number: 38-06031 Submission Orig. of Revision ECN Description of Change Date Change ** 110171 10/21/01 SZV Change from Spec number: 38-06031 *A 128959 09/03/03 JFU Added CY7C136-55NI to Order Information *B 236748 See ECN YDT Removed cross information from features section *C 393184 See ECN YIM Added Pb-Free Logo Added Pb-Free parts
