ページ1に含まれる内容の要旨
ADVANCE
CY14E108L, CY14E108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns access times The Cypress CY14E108L/CY14E108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 1024K x 8 (CY14E108L) or 512K x 16
organized as 1024K words of 8 bits each or 512K words of 16
(CY14E108N)
bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliab
ページ2に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Pinouts Figure 1. Pin Diagram - 48 FBGA 48-FBGA 48-FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 4 2 3 5 6 1 2 4 3 5 6 A A OE A NC A A A BLE NC OE NC 0 1 2 A 0 1 2 A DQ8 A NC BHE A CE DQ0 B A A 4 NC CE NC B 3 3 4 A A DQ2 C A A C DQ9 DQ10 DQ1 DQ0 NC NC DQ4 5 6 5 6 A V A V A DQ3 V A V SS DQ11 7 CC D SS DQ1 7 DQ5 CC D 17 17 V A V V A V CC DQ12 V DQ4 SS E CC DQ2 V DQ6 SS E 16 16 CAP CAP F A A F DQ14 DQ13 A A DQ6 DQ3 NC DQ7 DQ5 14 15 NC 14 15 [2] A
ページ3に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Pin Definitions Pin Name IO Type Description A – A Input Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration. 0 19 A – A Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration. 0 18 DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation. DQ0 – DQ15 Bidirectional Data IO Lines for x16 Configuration. Used as input or outpu
ページ4に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N To reduce unnecessary nonvolatile stores, AutoStore and Device Operation Hardware Store operations are ignored unless at least one The CY14E108L/CY14E108N nvSRAM is made up of two WRITE operation has taken place since the most recent STORE functional components paired in the same physical cell. They are or RECALL cycle. Software initiated STORE cycles are an SRAM memory cell and a nonvolatile QuantumTrap cell. The performed regardless of whether a WRITE operation has
ページ5に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N is disabled. It is important to use READ cycles and not WRITE Software STORE cycles in the sequence, although it is not necessary that OE be Transfer data from the SRAM to the nonvolatile memory with a LOW for a valid sequence. After the t cycle time is fulfilled, STORE software address sequence. The CY14B108L/CY14B108N the SRAM is activated again for the READ and WRITE operation. software STORE cycle is initiated by executing sequential CE controlled READ cycles fro
ページ6に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Table 1. Mode Selection (continued) A15 - A0 Mode IO Power CE WE OE [3,4,5] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Store Output High Z [3,4,5] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Outpu
ページ7に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260 °C [6] Storage Temperature ................................. –65 °C to +150 °C Output Short Circuit Current ...................................
ページ8に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Capacitance [9] In the following table, the capacitance parameters are listed . Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 14 pF IN A V = 0 to 3.0V CC C Output Capacitance 14 pF OUT Thermal Resistance [9] In the following table, the thermal resistance parameters are listed . Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit Θ Thermal Resistance Test conditions follow standard test methods 28.82 31.
ページ9に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N AC Switching Characteristics In the following table, the AC switching characteristics are listed. Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [10] t t Read Cycle Time 20 25 45 ns RC RC [11] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE t t Output Hold After Address Change 3 3 3 ns OHA OH [12] t t
ページ10に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N AutoStore and Power Up RECALL CY14E108L/CY14E108N Parameters Description Unit Min Max [14] t Power Up RECALL Duration 20 ms HRECALL [15] t STORE Cycle Duration 15 ms STORE V Low Voltage Trigger Level 4.4 V SWITCH t VCC Rise Time 150 μs VCCRISE Software Controlled STORE and RECALL Cycle [16, 17] In the following table, the software controlled STORE/RECALL cycle parameters are listed. 20ns 25ns 45ns Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL I
ページ11に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Switching Waveforms (continued) [10, 21, 23] Figure 6. SRAM Read Cycle #2: CE and OE Controlled t RC ADDRESS t ACE t PD CE t LZCE t HZCE OE t HZOE t DOE t LZOE BHE , BLE t HZCE t HZBE t DBE t LZBE DQ (DATA OUT) DATA VALID ACTIVE t PU STANDBY ICC [13, 21, 22, 23] Figure 7. SRAM Write Cycle #1: WE Controlled t WC ADDRESS t HA t SCE CE t AW t SA tPWE WE t BW BHE , BLE t tHD SD DATA VALID DATA IN t HZWE t LZWE HIGH IMPEDANCE DATA OUT PREVIOUS DATA Notes 22. CE or
ページ12に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Switching Waveforms (continued) [13, 21, 22, 23] Figure 8. SRAM Write Cycle #2: CE Controlled t WC ADDRESS t SA t SCE CE t HA t AW t WE PWE t BW BHE , BLE t t SD HD DATA IN DATA VALID HIGH IMPEDANCE DATA OUT [24] Figure 9. AutoStore or Power Up RECALL STORE occurs only No STORE occurs if a SRAM write without atleast one has happened SRAM write V CC V SWITCH tVCCRISE AutoStore t t STORE STORE POWER-UP RECALL t t HRECALL HRECALL Read & Write Inhibited Note 24. Re
ページ13に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Switching Waveforms (continued) [17] Figure 10. CE Controlled Software STORE/RECALL Cycle [17] Figure 11. OE Controlled Software STORE/RECALL Cycle t t RC RC ADDRESS # 1 ADDRESS # 6 ADDRESS CE t t AS CW OE t GHAX tSTORE / t RECALL HIGH IMPEDANCE DATA VALID DQ (DATA) DATA VALID Document Number: 001-45524 Rev. *A Page 13 of 20 [+] Feedback
ページ14に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Switching Waveforms (continued) [20] Figure 12. Hardware STORE Cycle [18, 19] Figure 13. Soft Sequence Processing t t SS SS Document Number: 001-45524 Rev. *A Page 14 of 20 [+] Feedback
ページ15に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14E108L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14E108L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14E108L-ZS20XI 51-85087 44-pin TSOP II CY14E108L-BA20XCT 51-85128 48-ball FBGA Commercial CY14E108L-BA20XIT 51-85128 48-ball FBGA Industrial CY14E108L-BA20XI 51-85128 48-ball FBGA CY14E108L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14E108L-ZSP20XIT 51-85160 54-pin
ページ16に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14E108L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14E108L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14E108L-ZS45XI 51-85087 44-pin TSOP II CY14E108L-BA45XCT 51-85128 48-ball FBGA Commercial CY14E108L-BA45XIT 51-85128 48-ball FBGA Industrial CY14E108L-BA45XI 51-85128 48-ball FBGA CY14E108L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14E108L-ZSP45XIT 51-
ページ17に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Package Diagrams Figure 14. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document Number: 001-45524 Rev. *A Page 17 of 20 [+] Feedback 1.194 (0.047) 0.991 (0.039)
ページ18に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Package Diagrams (continued) Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85128-*D Document Number: 001-45524 Rev. *A Page 18 of 20 [+] Feedback 0.25 C 10.00±0.10 0.36 0.53±0.05 0.21±0.05 1.20 MAX 0.15 C 10.00±0.10 5.25 0.75 2.625
ページ19に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Package Diagrams (continued) Figure 16. 54-Pin TSOP II (51-85160) 51-85160-** Document Number: 001-45524 Rev. *A Page 19 of 20 [+] Feedback
ページ20に含まれる内容の要旨
ADVANCE CY14E108L, CY14E108N Document History Page Document Title: CY14E108L/CY14E108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001- 45524 Submission Orig. of REV. ECN NO. Description of Change Date Change ** 2428826 See ECN GVCH New Data Sheet ** 2520023 06/23/08 GVCH/PYRS Updated I for tRC=20ns, 25ns and 45ns access speed for both CC1 industrial and Commecial temperature Grade Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II packages Changed t value from
