ページ1に含まれる内容の要旨
STK11C68-5 (SMD5962-92324)
64 Kbit (8K x 8) SoftStore nvSRAM
Features Functional Description
■ 35 ns, 45 ns, and 55 ns access times The Cypress STK11C68-5 is a 64 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
■ Pin compatible with industry standard SRAMs
nonvolatile elements incorporate QuantumTrap technology to
produce the world’s most reliable nonvolatile memory. The
■ Software initiated nonvolatile STORE
SRAM provides unlimited read and write cycles, while
■
ページ2に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Pinouts Figure 2. Pin Diagram - 28-Pin LLC Figure 1. Pin Diagram - 28-Pin DIP Pin Definitions Pin Name Alt I/O Type Description A –A Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. 0 12 DQ -DQ Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation. 0 7 Input Write Enable Input, Active LOW. When the chip is enabled and WE
ページ3に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) The software sequence is clocked with CE controlled Reads. Device Operation When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that The STK11C68-5 is a versatile memory chip that provides Read cycles and not Write cycles are used in the sequence. It is several modes of operation. The STK11C68-5 can operate as a not necessary that OE is LOW for a valid sequence. After the standard 8K x 8 SRAM. It has an
ページ4に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Figure 4. Current Versus Cycle Time (Write) Low Average Active Power CMOS technology provides the STK11C68-5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 and Figure 4 shows the relationship between I and Read or Write cycle time. Worst case current CC consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is draw
ページ5に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Voltage on DQ ...................................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation ......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC Output Current (1 output at a time, 1s duration).... 15 mA device. These user guidelines are not tested. Storage Temperature ................................. –65 °C to +150 °C Operating Range Temperature under bias.......................
ページ6に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Thermal Resistance [3] In this table, the thermal resistance parameters are listed. Parameter Description Test Conditions 28-CDIP 28-LCC Unit Θ Thermal Resistance Test conditions follow standard test methods and proce- TBD TBD °C/W JA (Junction to Ambient) dures for measuring thermal impedance, per EIA / JESD51. Θ Thermal Resistance TBD TBD °C/W JC (Junction to Case) Figure 5. AC Test Loads R1 480 Ω 5.0V Output R2 30 pF 255 Ω AC Test Conditions Input Pulse Levels...
ページ7に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) AC Switching Characteristics SRAM Read Cycle Parameter 35 ns 45 ns 55 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Chip Enable Access Time 35 45 55 ns ACE ELQV [4] t Read Cycle Time 35 45 55 ns t AVAV, RC t ELEH [5] t Address Access Time 35 45 55 ns t AVQV AA t t Output Enable to Data Valid 15 20 35 ns DOE GLQV [5] t Output Hold After Address Change 5 5 5 ns t AXQX OHA [6] t Chip Enable to Output Active 5 5 5 ns t ELQX LZCE [6] t Chip Di
ページ8に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) SRAM Write Cycle Parameter 35 ns 45 ns 55 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Write Cycle Time 35 45 55 ns WC AVAV t t t Write Pulse Width 25 30 45 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 25 30 45 ns SCE ELWH, ELEH t t t Data Setup to End of Write 12 15 30 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 25 30 45 ns AW AVWH, AVEH t t t Address Setup to Start of
ページ9に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) AutoStore INHIBIT or Power Up RECALL STK11C68-5 Parameter Alt Description Unit Min Max [9] t Power up RECALL Duration 550 μs t RESTORE HRECALL t t STORE Cycle Duration 10 ms STORE HLHZ V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.6 V RESET Figure 10. AutoStore INHIBIT/Power Up RECALL V CC 5V V SWITCH V RESET STORE INHIBIT POWER-UPRECALL t HRECALL DQ (DATA OUT) POWER-UP BROWN OUT BROWN OUT BROWN OUT RECALL STORE INHIBIT STORE INHIBIT STO
ページ10に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Software Controlled STORE/RECALL Cycle [10, 11] The software controlled STORE/RECALL cycle follows. 35 ns 45 ns 55 ns Parameter Alt Description Unit Min Max Min Max Min Max t t STORE/RECALL Initiation Cycle Time 35 45 55 ns RC AVAV [10] t Address Setup Time 0 0 0 ns t AVEL SA [10] t Clock Pulse Width 25 30 35 ns t ELEH CW [10] t Address Hold Time 20 20 20 ns t ELAX HACE [10] RECALL Duration 20 20 20 μs t RECALL Switching Waveform [10] Figure 11. CE Controlled Softwa
ページ11に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Part Numbering Nomenclature STK11C68 - 5 C 45 M Temperature Range: M - Military (-55 to 125°C) Speed: 35 - 35 ns 45 - 45 ns 55 - 55 ns Package: C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (Solder dip finish) L = Ceramic 28-pin LLC Retention / Endurance 5 5 = Military (10 years or 10 cycles) SMD5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Case Outlin
ページ12に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 35 STK11C68-5C35M 001-51695 28-Pin CDIP (300 mil) Military STK11C68-5K35M 001-51695 28-Pin CDIP (300 mil) STK11C68-5L35M 001-51696 28-Pin LCC (350 mil) 45 STK11C68-5C45M 001-51695 28-Pin CDIP (300 mil) STK11C68-5K45M 001-51695 28-Pin CDIP (300 mil) STK11C68-5L45M 001-51696 28-Pin LCC (350 mil) 55 STK11C68-5C55M 001-51695 28-Pin CDIP (300 mil) STK11C68-5K55M 001-51695 28-Pin CDIP
ページ13に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Package Diagrams Figure 12. 28-Pin (300-Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-51001 Rev. *A Page 13 of 15 [+] Feedback
ページ14に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Package Diagrams (continued) Figure 13. 28-Pad (350-Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD 001-51696 ** Document Number: 001-51001 Rev. *A Page 14 of 15 [+] Feedback
ページ15に含まれる内容の要旨
STK11C68-5 (SMD5962-92324) Document History Page Document Title: STK11C68-5 (SMD5962-92324) 64 Kbit (8K x 8) SoftStore nvSRAM Document Number: 001-51001 Submission Rev. ECN No. Orig. of Change Description of Change Date ** 2666844 GVCH/PYRS 03/02/09 New data sheet *A 2685053 GVCH 04/07/2009 Added part numbers: STK11C68-5K45M and STK11C68-5K55M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufactu
